xspusb.vhd

the vhdl model of usb. it is very helpful.

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-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--     
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--     
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--     
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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-- Project:      Full-Speed USB 1.1 Function Controller
-- File:         xspUSB.vhd
-- Description:  XSP-010 board, 8051-to-USB glue logic.
-- Version:      FB, 2000jul29
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library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity xspUSB is
	port(
		-- 8051 signals
		A:         in  STD_LOGIC_VECTOR(15 downto 0);     -- address bus
		DIN:       in  STD_LOGIC_VECTOR(7 downto 0);      -- data in
		DOUT:      out STD_LOGIC_VECTOR(7 downto 0);      -- data out
		DDRV:      out STD_LOGIC;                         -- data out enable
		RD:        in  STD_LOGIC;                         -- read strobe
		WR:        in  STD_LOGIC;                         -- write strobe
		-- usb fifo signals
		uc_adx:    out STD_LOGIC_VECTOR(2 downto 0);      -- address bus
		uc_drd:    in  STD_LOGIC_VECTOR(7 downto 0);      -- data read
		uc_dwr:    out STD_LOGIC_VECTOR(7 downto 0);      -- data write
		uc_wren:   out STD_LOGIC;                         -- write enable
		-- usb endpoint controller
		uc_ctrl:   out STD_LOGIC_VECTOR(7 downto 0);      -- control word
		uc_status: in  STD_LOGIC_VECTOR(7 downto 0);      -- status word
		uc_wrctrl: out STD_LOGIC;                         -- control write enable
		-- usb device address
		uc_dadx:   out STD_LOGIC_VECTOR(6 downto 0);      -- device address
		uc_wradx:  out STD_LOGIC                          -- write enable
		);
end xspUSB;

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architecture BHV of xspUSB is
	signal fifo: STD_LOGIC;
	signal ctrl: STD_LOGIC;
	signal dadx: STD_LOGIC;
begin
	
	-- address decoding
	fifo<= '1' when A(15 downto 12)= "1110" else '0'; -- 0xExxx
	ctrl<= '1' when A(15 downto 12)= "1101" else '0'; -- 0xDxxx
	dadx<= '1' when A(15 downto 12)= "1100" else '0'; -- 0xCxxx
	
	DDRV<= '1' when (fifo= '1' or ctrl= '1' or dadx= '1') and rd= '0' else '0';
	
	-- fifo
	uc_adx   <= A(2 downto 0) when fifo= '1' else (others=> '-');
	DOUT     <= uc_drd when fifo= '1' and rd= '0' else (others=> 'Z');
	uc_dwr   <= DIN;
	uc_wren  <= '1' when fifo= '1' and wr= '0' else '0';
	
	-- endpoint controller
	uc_ctrl  <= DIN;
	DOUT     <= uc_status when ctrl= '1' and rd= '0' else (others=> 'Z');
	uc_wrctrl<= '1' when ctrl= '1' and wr= '0' else '0';
	
	-- usb device address
	uc_dadx  <= DIN(6 downto 0);
	uc_wradx <= '1' when dadx= '1' and wr= '0' else '0';
	
end BHV;

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