usbep0.vhd

the vhdl model of usb. it is very helpful.

	Usie_Utrac_Upak_Upakr_rxfrm_reg_8 : DFF_CLR_PRE port map ( D => N600 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_8 
		);
	Usie_Utrac_Upak_Upakr_rxfrm_reg_9 : DFF_CLR_PRE port map ( D => N606 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_9 
		);
	Usie_Utrac_Upak_Upakr_rxfrm_reg_10 : DFF_CLR_PRE port map ( D => N612 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_10 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_0 : DFF_CLR_PRE port map ( D => N618 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_0 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_1 : DFF_CLR_PRE port map ( D => N624 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_1 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_2 : DFF_CLR_PRE port map ( D => N630 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_2 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_3 : DFF_CLR_PRE port map ( D => N636 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_3 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_4 : DFF_CLR_PRE port map ( D => N642 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_4 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_5 : DFF_CLR_PRE port map ( D => N648 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_5 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_6 : DFF_CLR_PRE port map ( D => N654 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_6 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_7 : DFF_CLR_PRE port map ( D => N660 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_7 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_8 : DFF_CLR_PRE port map ( D => N666 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_8 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_9 : DFF_CLR_PRE port map ( D => N672 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_9 
		);
	Usie_Utrac_Upak_Upakr_rxadep_reg_10 : DFF_CLR_PRE port map ( D => N678 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_BUS1153_10 
		);
	Usie_Utrac_Upak_Upakt_Spakt_reg_0 : DFF_CLR_PRE port map ( D => N684 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakt_Spakt_0 
		);
	Usie_Utrac_Upak_Upakt_Spakt_reg_2 : DFF_CLR_PRE port map ( D => N690 
		, C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Upakt_Spakt_2 
		);
	Usie_Utrac_Upak_Upakt_Spakt_reg_1 : DFF_CLR_PRE port map ( D => N696 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakt_Spakt_1 
		);
	Usie_Utrac_Upak_Upakt_PID_reg_0 : DFF_CLR_PRE port map ( D => N702 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakt_PID_0 
		);
	Usie_Utrac_Upak_Upakt_PID_reg_1 : DFF_CLR_PRE port map ( D => N708 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakt_PID_1 
		);
	Usie_Utrac_Upak_Upakt_PID_reg_2 : DFF_CLR_PRE port map ( D => N714 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakt_PID_2 
		);
	Usie_Utrac_Upak_Upakt_PID_reg_3 : DFF_CLR_PRE port map ( D => N720 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakt_PID_3 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crcen_reg : DFF_CLR_PRE port map ( D => 
		N727 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Ucrc16_crcen 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_0 : DFF_CLR_PRE port map ( D => 
		N734 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_1 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_1 : DFF_CLR_PRE port map ( D => 
		N741 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_2 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_2 : DFF_CLR_PRE port map ( D => 
		N748 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_3 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_3 : DFF_CLR_PRE port map ( D => 
		N755 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_4 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_4 : DFF_CLR_PRE port map ( D => 
		N762 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_5 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_5 : DFF_CLR_PRE port map ( D => 
		N769 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_6 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_6 : DFF_CLR_PRE port map ( D => 
		N776 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_7 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_7 : DFF_CLR_PRE port map ( D => 
		N783 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_8 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_8 : DFF_CLR_PRE port map ( D => 
		N790 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_9 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_9 : DFF_CLR_PRE port map ( D => 
		N797 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_10 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_10 : DFF_CLR_PRE port map ( D => 
		N804 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_11 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_11 : DFF_CLR_PRE port map ( D => 
		N811 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_12 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_12 : DFF_CLR_PRE port map ( D => 
		N818 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_13 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_13 : DFF_CLR_PRE port map ( D => 
		N825 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_14 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_14 : DFF_CLR_PRE port map ( D => 
		N832 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_shift_15 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_15 : DFF_CLR_PRE port map ( D => 
		N839 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Ucrc16_crc_15 
		);
	Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_reg_0 : DFF_CLR_PRE port map ( D 
		=> N846 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => 
		Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0 );
	Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_reg_1 : DFF_CLR_PRE port map ( D 
		=> N852 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => 
		Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_1 );
	Usie_Utrac_Upak_Usp_Uspr_valid_reg : DFF_CLR_PRE port map ( D => N858 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspr_valid 
		);
	Usie_Utrac_Upak_Usp_Uspr_count_reg_0 : DFF_CLR_PRE port map ( D => 
		N864 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Uspr_count_0 
		);
	Usie_Utrac_Upak_Usp_Uspr_count_reg_1 : DFF_CLR_PRE port map ( D => 
		N870 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Uspr_count_1 
		);
	Usie_Utrac_Upak_Usp_Uspr_count_reg_2 : DFF_CLR_PRE port map ( D => 
		N876 , C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Uspr_count_2 
		);
	Usie_Utrac_Upak_Usp_Uspr_shift_reg_0 : DFF_CLR_PRE port map ( D => 
		N882 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_BUS511_0 
		);
	Usie_Utrac_Upak_Usp_Uspr_shift_reg_1 : DFF_CLR_PRE port map ( D => 
		N888 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_BUS511_1 
		);
	Usie_Utrac_Upak_Usp_Uspr_shift_reg_2 : DFF_CLR_PRE port map ( D => 
		N894 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_BUS511_2 
		);
	Usie_Utrac_Upak_Usp_Uspr_shift_reg_3 : DFF_CLR_PRE port map ( D => 
		N900 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_BUS511_3 
		);
	Usie_Utrac_Upak_Usp_Uspr_shift_reg_4 : DFF_CLR_PRE port map ( D => 
		N906 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_BUS511_4 
		);
	Usie_Utrac_Upak_Usp_Uspr_shift_reg_5 : DFF_CLR_PRE port map ( D => 
		N912 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_BUS511_5 
		);
	Usie_Utrac_Upak_Usp_Uspr_shift_reg_6 : DFF_CLR_PRE port map ( D => 
		N918 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_BUS511_6 
		);
	Usie_Utrac_Upak_Usp_Uspr_shift_reg_7 : DFF_CLR_PRE port map ( D => 
		N925 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_BUS511_7 
		);
	Usie_Utrac_Upak_Usp_Uspt_valid_reg : DFF_CLR_PRE port map ( D => N932 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_valid 
		);
	Usie_Utrac_Upak_Usp_Uspt_count_reg_2 : DFF_CLR_PRE port map ( D => 
		N939 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_count_2 
		);
	Usie_Utrac_Upak_Usp_Uspt_count_reg_1 : DFF_CLR_PRE port map ( D => 
		N946 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_count_1 
		);
	Usie_Utrac_Upak_Usp_Uspt_count_reg_0 : DFF_CLR_PRE port map ( D => 
		N953 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_count_0 
		);
	Usie_Utrac_Upak_Usp_Uspt_shift_reg_0 : DFF_CLR_PRE port map ( D => 
		N960 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_NET1109 
		);
	Usie_Utrac_Upak_Usp_Uspt_shift_reg_1 : DFF_CLR_PRE port map ( D => 
		N967 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_shift_1 
		);
	Usie_Utrac_Upak_Usp_Uspt_shift_reg_2 : DFF_CLR_PRE port map ( D => 
		N974 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_shift_2 
		);
	Usie_Utrac_Upak_Usp_Uspt_shift_reg_3 : DFF_CLR_PRE port map ( D => 
		N981 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_shift_3 
		);
	Usie_Utrac_Upak_Usp_Uspt_shift_reg_4 : DFF_CLR_PRE port map ( D => 
		N988 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_shift_4 
		);
	Usie_Utrac_Upak_Usp_Uspt_shift_reg_5 : DFF_CLR_PRE port map ( D => 
		N995 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_shift_5 
		);
	Usie_Utrac_Upak_Usp_Uspt_shift_reg_6 : DFF_CLR_PRE port map ( D => 
		N1002 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_shift_6 
		);
	Usie_Utrac_Upak_Usp_Uspt_shift_reg_7 : DFF_CLR_PRE port map ( D => 
		N1009 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Uspt_shift_7 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_reg_2 : DFF_CLR_PRE port map ( 
		D => N1015 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q 
		=> Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2 );
	Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_reg_0 : DFF_CLR_PRE port map ( 
		D => N1021 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q 
		=> Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_0 );
	Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2_reg : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_NET519 , C => clk12 , CLR => rst , PRE => 
		Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2 );
	Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_reg : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C3_N5 , C => clk12 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_reg_1 : DFF_CLR_PRE port map ( 
		D => N1039 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q 
		=> Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1 );
	Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_reg : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C3_N3 , C => clk12 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Unrzit_stuff2_reg : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C2_N3 , C => clk12 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Unrzit_stuff2 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_reg_1 : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N9 , C => clk12 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_reg_0 : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N6 , C => clk12 , CLR 
		=> Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_0 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_reg_2 : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N15 , C => clk12 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_reg_2 : DFF_CLR_PRE port 
		map ( D => N1075 , C => clk48 , CLR => Ufifox_adx_3 , PRE => rst 
		, Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2 );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_reg_0 : DFF_CLR_PRE port 
		map ( D => N1081 , C => clk48 , CLR => Ufifox_adx_3 , PRE => rst 
		, Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_0 );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a_reg : DFF_CLR_PRE port map ( 
		D => urxd , C => clk48 , CLR => rst , PRE => Ufifox_adx_3 , Q => 
		Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_reg_0 : DFF_CLR_PRE port 
		map ( D => N1093 , C => clk48 , CLR => rst , PRE => Ufifox_adx_3 
		, Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_0 );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12o_reg : DFF_CLR_PRE port 
		map ( D => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C23_N12 , C => 
		clk48 , CLR => rst , PRE => Ufifox_adx_3 , Q => clk12o );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_reg : DFF_CLR_Cb_PRE port map ( 
		D => urxd , C => clk48 , CLR => rst , PRE => Ufifox_adx_3 , Q => 
		Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_reg_1 : DFF_CLR_PRE port 
		map ( D => N1111 , C => clk48 , CLR => rst , PRE => Ufifox_adx_3 
		, Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1 );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_reg_3 : DFF_CLR_PRE port 
		map ( D => N1117 , C => clk48 , CLR => Ufifox_adx_3 , PRE => rst 
		, Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3 );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_reg_1 : DFF_CLR_PRE port 
		map ( D => N1123 , C => clk48 , CLR => rst , PRE => Ufifox_adx_3 
		, Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1 );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_reg_0 : DFF_CLR_PRE port map ( 
		D => N1550 , C => clk48 , CLR => rst , PRE => Ufifox_adx_3 , Q 
		=> Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0 );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_reg_1 : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_N281 , C => clk48 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_reg_1 : DFF_CLR_PRE port 
		map ( D => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N27 , C => 
		clk48 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_1 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_reg : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se04 , C => clk48 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_reg : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop4 , C => clk48 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_reg_1 : DFF_CLR_PRE port 
		map ( D => N1160 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 
		, Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1 );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_reg : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop2 , C => clk48 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_frxen_reg : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_0 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_NET519 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_reg : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se02 , C => clk48 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop2_reg : DFF_CLR_PRE port map ( 
		D => N1548 , C => clk48 , CLR => rst , PRE => Ufifox_adx_3 , Q 
		=> Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop2 );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se02_reg : DFF_CLR_PRE port map ( 
		D => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_N84 , C => clk48 , CLR 
		=> rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se02 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_reg_0 : DFF_CLR_PRE port 
		map ( D => N1197 , C => clk12 , CLR => rst , PRE => Ufifox_adx_3 
		, Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_0 );
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_reg_2 : DFF_CLR_PRE port 
		map ( D => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N15 , C => 
		clk48 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2 
		);
	Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se04_reg : DFF_CLR_PRE port map ( 
		D =>