usbep0.vhd

the vhdl model of usb. it is very helpful.

	, syn32681 : std_logic ;
	
begin
	rxen <= rxen0 ;
	sof_trac <= sof_trac0 ;
	in_trac(0) <= in_trac_0 ;
	out_trac(0) <= out_trac_0 ;
	rxd(7) <= rxd_7 ;
	rxd(6) <= rxd_6 ;
	rxd(5) <= rxd_5 ;
	rxd(4) <= rxd_4 ;
	rxd(3) <= rxd_3 ;
	rxd(2) <= rxd_2 ;
	rxd(1) <= rxd_1 ;
	rxd(0) <= rxd_0 ;
	rxfrm(10) <= rxfrm_10 ;
	rxfrm(9) <= rxfrm_9 ;
	rxfrm(8) <= rxfrm_8 ;
	rxfrm(7) <= rxfrm_7 ;
	rxfrm(6) <= rxfrm_6 ;
	rxfrm(5) <= rxfrm_5 ;
	rxfrm(4) <= rxfrm_4 ;
	rxfrm(3) <= rxfrm_3 ;
	rxfrm(2) <= rxfrm_2 ;
	rxfrm(1) <= rxfrm_1 ;
	rxfrm(0) <= rxfrm_0 ;
	setup_trac(0) <= setup_trac_0 ;
	uc_drd(7) <= BUS63_7 ;
	uc_drd(6) <= BUS63_6 ;
	uc_drd(5) <= BUS63_5 ;
	uc_drd(4) <= BUS63_4 ;
	uc_drd(3) <= BUS63_3 ;
	uc_drd(2) <= BUS63_2 ;
	uc_drd(1) <= BUS63_1 ;
	uc_drd(0) <= BUS63_0 ;
	Ufifox_U0 : lbx16x8 port map ( A(3) => Ufifox_adx_3 , A(2) => BUS59_2 
		, A(1) => BUS59_1 , A(0) => BUS59_0 , DI(7) => BUS67_7 , DI(6) 
		=> BUS67_6 , DI(5) => BUS67_5 , DI(4) => BUS67_4 , DI(3) => BUS67_3 
		, DI(2) => BUS67_2 , DI(1) => BUS67_1 , DI(0) => BUS67_0 , WR_EN 
		=> NET71 , WR_CLK => clk12 , DO(7) => BUS63_7 , DO(6) => BUS63_6 
		, DO(5) => BUS63_5 , DO(4) => BUS63_4 , DO(3) => BUS63_3 , DO(2) 
		=> BUS63_2 , DO(1) => BUS63_1 , DO(0) => BUS63_0 );
	Uep0ctrl_uc_status_reg_1 : DFF_CLR_PRE port map ( D => Uep0ctrl_C34_N20 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => uc_status(1) 
		);
	Uep0ctrl_Sfifo_reg_0 : DFF_CLR_PRE port map ( D => N11 , C => clk12 
		, CLR => Ufifox_adx_3 , PRE => rst , Q => Uep0ctrl_Sfifo_0 );
	Uep0ctrl_uc_status_reg_5 : DFF_CLR_PRE port map ( D => Uep0ctrl_N219 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => uc_status(5) 
		);
	Uep0ctrl_uc_status_reg_7 : DFF_CLR_PRE port map ( D => Uep0ctrl_N210 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => uc_status(7) 
		);
	Uep0ctrl_uc_status_reg_3 : DFF_CLR_PRE port map ( D => Uep0ctrl_C34_N36 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => uc_status(3) 
		);
	Uep0ctrl_Sfifo_reg_2 : DFF_CLR_PRE port map ( D => N35 , C => clk12 
		, CLR => Ufifox_adx_3 , PRE => rst , Q => Uep0ctrl_Sfifo_2 );
	Uep0ctrl_stall_en_reg : DFF_CLR_PRE port map ( D => N41 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_stall_en );
	Uep0ctrl_out_en_reg : DFF_CLR_PRE port map ( D => N48 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_out_en );
	Uep0ctrl_uc_wrctrl2_reg : DFF_CLR_PRE port map ( D => uc_wrctrl , C 
		=> clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_uc_wrctrl2 
		);
	Uep0ctrl_toggle_reg : DFF_CLR_PRE port map ( D => N61 , C => clk12 
		, CLR => Ufifox_adx_3 , PRE => rst , Q => TG_0 );
	Uep0ctrl_Sfifo_reg_3 : DFF_CLR_PRE port map ( D => N67 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_Sfifo_3 );
	Uep0ctrl_uc_status_reg_2 : DFF_CLR_PRE port map ( D => Uep0ctrl_C34_N28 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => uc_status(2) 
		);
	Uep0ctrl_uc_status_reg_6 : DFF_CLR_PRE port map ( D => Uep0ctrl_C34_N53 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => uc_status(6) 
		);
	Uep0ctrl_uc_status_reg_4 : DFF_CLR_PRE port map ( D => Ufifox_adx_3 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => uc_status(4) 
		);
	Uep0ctrl_in_en_reg : DFF_CLR_PRE port map ( D => N94 , C => clk12 , 
		CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_in_en );
	Uep0ctrl_setup_en_reg : DFF_CLR_PRE port map ( D => N101 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_setup_en );
	Uep0ctrl_Sfifo_reg_1 : DFF_CLR_PRE port map ( D => N107 , C => clk12 
		, CLR => Ufifox_adx_3 , PRE => rst , Q => Uep0ctrl_Sfifo_1 );
	Uep0ctrl_uc_status_reg_0 : DFF_CLR_PRE port map ( D => Uep0ctrl_C34_N12 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => uc_status(0) 
		);
	Uep0ctrl_adx_cnt_reg_0 : DFF_CLR_PRE port map ( D => N119 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_adx_cnt_0 );
	Uep0ctrl_adx_cnt_reg_1 : DFF_CLR_PRE port map ( D => N125 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_adx_cnt_1 );
	Uep0ctrl_adx_cnt_reg_2 : DFF_CLR_PRE port map ( D => N131 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_adx_cnt_2 );
	Uep0ctrl_adx_cnt_reg_3 : DFF_CLR_PRE port map ( D => N137 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_adx_cnt_3 );
	Uep0ctrl_n_reg_0 : DFF_CLR_PRE port map ( D => N143 , C => clk12 , 
		CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_n_0 );
	Uep0ctrl_n_reg_1 : DFF_CLR_PRE port map ( D => N149 , C => clk12 , 
		CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_n_1 );
	Uep0ctrl_n_reg_2 : DFF_CLR_PRE port map ( D => N155 , C => clk12 , 
		CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_n_2 );
	Uep0ctrl_n_reg_3 : DFF_CLR_PRE port map ( D => N161 , C => clk12 , 
		CLR => rst , PRE => Ufifox_adx_3 , Q => Uep0ctrl_n_3 );
	Usie_Urst_usb_reset_reg : DFF_CLR_PRE port map ( D => Usie_Urst_C0_N3 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_NET2015 
		);
	Usie_Urst_cnt_reg_0 : DFF_CLR_PRE port map ( D => N173 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Urst_cnt_0 );
	Usie_Urst_cnt_reg_1 : DFF_CLR_PRE port map ( D => N179 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Urst_cnt_1 );
	Usie_Urst_cnt_reg_2 : DFF_CLR_PRE port map ( D => N185 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Urst_cnt_2 );
	Usie_Urst_cnt_reg_3 : DFF_CLR_PRE port map ( D => N191 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Urst_cnt_3 );
	Usie_Urst_cnt_reg_4 : DFF_CLR_PRE port map ( D => N197 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Urst_cnt_4 );
	Usie_Urst_cnt_reg_5 : DFF_CLR_PRE port map ( D => N203 , C => clk12 
		, CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Urst_cnt_5 );
	Usie_Uepdec_tmp_addr_reg_0 : DFF_CLR_PRE port map ( D => N209 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_tmp_addr_0 
		);
	Usie_Uepdec_tmp_addr_reg_1 : DFF_CLR_PRE port map ( D => N215 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_tmp_addr_1 
		);
	Usie_Uepdec_tmp_addr_reg_2 : DFF_CLR_PRE port map ( D => N221 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_tmp_addr_2 
		);
	Usie_Uepdec_tmp_addr_reg_3 : DFF_CLR_PRE port map ( D => N227 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_tmp_addr_3 
		);
	Usie_Uepdec_tmp_addr_reg_4 : DFF_CLR_PRE port map ( D => N233 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_tmp_addr_4 
		);
	Usie_Uepdec_tmp_addr_reg_5 : DFF_CLR_PRE port map ( D => N239 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_tmp_addr_5 
		);
	Usie_Uepdec_tmp_addr_reg_6 : DFF_CLR_PRE port map ( D => N245 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_tmp_addr_6 
		);
	Usie_Uepdec_dev_addr_reg_0 : DFF_CLR_PRE port map ( D => N251 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_dev_addr_0 
		);
	Usie_Uepdec_dev_addr_reg_1 : DFF_CLR_PRE port map ( D => N257 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_dev_addr_1 
		);
	Usie_Uepdec_dev_addr_reg_2 : DFF_CLR_PRE port map ( D => N263 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_dev_addr_2 
		);
	Usie_Uepdec_dev_addr_reg_3 : DFF_CLR_PRE port map ( D => N269 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_dev_addr_3 
		);
	Usie_Uepdec_dev_addr_reg_4 : DFF_CLR_PRE port map ( D => N275 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_dev_addr_4 
		);
	Usie_Uepdec_dev_addr_reg_5 : DFF_CLR_PRE port map ( D => N281 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_dev_addr_5 
		);
	Usie_Uepdec_dev_addr_reg_6 : DFF_CLR_PRE port map ( D => N287 , C => 
		clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Uepdec_dev_addr_6 
		);
	Usie_Utrac_Utracrt_setup_trac_reg : DFF_CLR_PRE port map ( D => N293 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_NET1039 
		);
	Usie_Utrac_Utracrt_Strac_reg_0 : DFF_CLR_PRE port map ( D => N299 , 
		C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Utracrt_Strac_0 
		);
	Usie_Utrac_Utracrt_out_trac_reg : DFF_CLR_PRE port map ( D => N305 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_NET1035 
		);
	Usie_Utrac_Utracrt_Strac_reg_2 : DFF_CLR_PRE port map ( D => N311 , 
		C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Utracrt_Strac_2 
		);
	Usie_Utrac_Utracrt_rxvalid2_reg : DFF_CLR_PRE port map ( D => Usie_Utrac_Utracrt_rxvalid1 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Utracrt_rxvalid2 
		);
	Usie_Utrac_Utracrt_Strac_reg_1 : DFF_CLR_PRE port map ( D => N323 , 
		C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Utracrt_Strac_1 
		);
	Usie_Utrac_Utracrt_in_trac_reg : DFF_CLR_PRE port map ( D => N329 , 
		C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_NET1024 
		);
	Usie_Utrac_Utracrt_txstrobe_reg : DFF_CLR_PRE port map ( D => N336 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Utracrt_txstrobe 
		);
	Usie_Utrac_Utracrt_sof_trac_reg : DFF_CLR_PRE port map ( D => N342 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => sof_trac0 
		);
	Usie_Utrac_Utracrt_rxvalid1_reg : DFF_CLR_PRE port map ( D => Usie_Utrac_NET230 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Utracrt_rxvalid1 
		);
	Usie_Utrac_Upak_Upakr_Srpak_reg_1 : DFF_CLR_PRE port map ( D => N354 
		, C => clk12 , CLR => Ufifox_adx_3 , PRE => rst , Q => Usie_Utrac_Upak_Upakr_Srpak_1 
		);
	Usie_Utrac_Upak_Upakr_Srpak_reg_2 : DFF_CLR_PRE port map ( D => N360 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_Srpak_2 
		);
	Usie_Utrac_Upak_Upakr_Srpak_reg_0 : DFF_CLR_PRE port map ( D => N366 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_Srpak_0 
		);
	Usie_Utrac_Upak_Upakr_rxd2_reg_0 : DFF_CLR_PRE port map ( D => N372 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxd_0 );
	Usie_Utrac_Upak_Upakr_rxd2_reg_1 : DFF_CLR_PRE port map ( D => N378 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxd_1 );
	Usie_Utrac_Upak_Upakr_rxd2_reg_2 : DFF_CLR_PRE port map ( D => N384 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxd_2 );
	Usie_Utrac_Upak_Upakr_rxd2_reg_3 : DFF_CLR_PRE port map ( D => N390 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxd_3 );
	Usie_Utrac_Upak_Upakr_rxd2_reg_4 : DFF_CLR_PRE port map ( D => N396 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxd_4 );
	Usie_Utrac_Upak_Upakr_rxd2_reg_5 : DFF_CLR_PRE port map ( D => N402 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxd_5 );
	Usie_Utrac_Upak_Upakr_rxd2_reg_6 : DFF_CLR_PRE port map ( D => N408 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxd_6 );
	Usie_Utrac_Upak_Upakr_rxd2_reg_7 : DFF_CLR_PRE port map ( D => N414 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxd_7 );
	Usie_Utrac_Upak_Upakr_rxd1_reg_0 : DFF_CLR_PRE port map ( D => N420 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_rxd1_0 
		);
	Usie_Utrac_Upak_Upakr_rxd1_reg_1 : DFF_CLR_PRE port map ( D => N426 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_rxd1_1 
		);
	Usie_Utrac_Upak_Upakr_rxd1_reg_2 : DFF_CLR_PRE port map ( D => N432 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_rxd1_2 
		);
	Usie_Utrac_Upak_Upakr_rxd1_reg_3 : DFF_CLR_PRE port map ( D => N438 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_rxd1_3 
		);
	Usie_Utrac_Upak_Upakr_rxd1_reg_4 : DFF_CLR_PRE port map ( D => N444 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_rxd1_4 
		);
	Usie_Utrac_Upak_Upakr_rxd1_reg_5 : DFF_CLR_PRE port map ( D => N450 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_rxd1_5 
		);
	Usie_Utrac_Upak_Upakr_rxd1_reg_6 : DFF_CLR_PRE port map ( D => N456 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_rxd1_6 
		);
	Usie_Utrac_Upak_Upakr_rxd1_reg_7 : DFF_CLR_PRE port map ( D => N462 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_rxd1_7 
		);
	Usie_Utrac_Upak_Upakr_rxden_reg_0 : DFF_CLR_PRE port map ( D => N468 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_rxden_0 
		);
	Usie_Utrac_Upak_Upakr_rxden_reg_1 : DFF_CLR_PRE port map ( D => N474 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_rxden_1 
		);
	Usie_Utrac_Upak_Upakr_pidreg_reg_0 : DFF_CLR_PRE port map ( D => N480 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_BUS222_0 
		);
	Usie_Utrac_Upak_Upakr_pidreg_reg_1 : DFF_CLR_PRE port map ( D => N486 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_BUS222_1 
		);
	Usie_Utrac_Upak_Upakr_pidreg_reg_2 : DFF_CLR_PRE port map ( D => N492 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_BUS222_2 
		);
	Usie_Utrac_Upak_Upakr_pidreg_reg_3 : DFF_CLR_PRE port map ( D => N498 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_BUS222_3 
		);
	Usie_Utrac_Upak_Upakr_adepfrm_reg_0 : DFF_CLR_PRE port map ( D => N504 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_adepfrm_0 
		);
	Usie_Utrac_Upak_Upakr_adepfrm_reg_1 : DFF_CLR_PRE port map ( D => N510 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_adepfrm_1 
		);
	Usie_Utrac_Upak_Upakr_adepfrm_reg_2 : DFF_CLR_PRE port map ( D => N516 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_adepfrm_2 
		);
	Usie_Utrac_Upak_Upakr_adepfrm_reg_3 : DFF_CLR_PRE port map ( D => N522 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_adepfrm_3 
		);
	Usie_Utrac_Upak_Upakr_adepfrm_reg_4 : DFF_CLR_PRE port map ( D => N528 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_adepfrm_4 
		);
	Usie_Utrac_Upak_Upakr_adepfrm_reg_5 : DFF_CLR_PRE port map ( D => N534 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_adepfrm_5 
		);
	Usie_Utrac_Upak_Upakr_adepfrm_reg_6 : DFF_CLR_PRE port map ( D => N540 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_adepfrm_6 
		);
	Usie_Utrac_Upak_Upakr_adepfrm_reg_7 : DFF_CLR_PRE port map ( D => N546 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => Usie_Utrac_Upak_Upakr_adepfrm_7 
		);
	Usie_Utrac_Upak_Upakr_rxfrm_reg_0 : DFF_CLR_PRE port map ( D => N552 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_0 
		);
	Usie_Utrac_Upak_Upakr_rxfrm_reg_1 : DFF_CLR_PRE port map ( D => N558 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_1 
		);
	Usie_Utrac_Upak_Upakr_rxfrm_reg_2 : DFF_CLR_PRE port map ( D => N564 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_2 
		);
	Usie_Utrac_Upak_Upakr_rxfrm_reg_3 : DFF_CLR_PRE port map ( D => N570 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_3 
		);
	Usie_Utrac_Upak_Upakr_rxfrm_reg_4 : DFF_CLR_PRE port map ( D => N576 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_4 
		);
	Usie_Utrac_Upak_Upakr_rxfrm_reg_5 : DFF_CLR_PRE port map ( D => N582 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_5 
		);
	Usie_Utrac_Upak_Upakr_rxfrm_reg_6 : DFF_CLR_PRE port map ( D => N588 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_6 
		);
	Usie_Utrac_Upak_Upakr_rxfrm_reg_7 : DFF_CLR_PRE port map ( D => N594 
		, C => clk12 , CLR => rst , PRE => Ufifox_adx_3 , Q => rxfrm_7 
		);