usbep0.vhd

the vhdl model of usb. it is very helpful.

--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--     
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--     
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--     
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--------------------------------------------------------------------------------
-- Project:      Full-Speed USB 1.1 Function Controller
-- File:         usbEP0.vhd
-- Description:  Behavioral Evaluation Model.
-- Version:      FB, 2000aug14
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity lbx16x8 is
	port (
		A: in std_logic_vector(3 downto 0);
		DI: in std_logic_vector(7 downto 0);
		WR_EN: in std_logic;
		WR_CLK: in std_logic;
		DO: out std_logic_vector(7 downto 0)
		);
end lbx16x8;

architecture Eval of lbx16x8 is
	type Tfifo is array (0 to 15) of std_logic_vector(7 downto 0);
	signal fifo: Tfifo;
	signal aint: integer range 0 to 15;
begin
	aint<= CONV_INTEGER(a);
	do<= fifo(aint);
	
	process(wr_clk)
	begin
		if rising_edge(wr_clk) then
			if wr_en= '1' then
				fifo(aint)<= di;
			end if;
		end if;
	end process;
	
end architecture;

library IEEE;
use IEEE.std_logic_1164.all;

entity DFF_CLR_PRE is
	port ( 
		D : in std_logic ;
		C : in std_logic ;
		CLR : in std_logic ;
		PRE : in std_logic ;
		Q : out std_logic );
end DFF_CLR_PRE ;

architecture Eval of DFF_CLR_PRE is
	
	signal synch_enable : std_logic ;
	
begin
	process ( C , CLR , PRE )
	begin
		if ( ( CLR = '1' ) and ( PRE = '1') ) then Q <= '0';
		elsif ( CLR = '1' ) then Q <= '0';
		elsif ( PRE = '1' ) then Q <= '1';
		elsif ( C'event and C = '1' ) then
			Q <= ( D );
		end if;
	end process;
	synch_enable <= ( '1' );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity DFF_CLR_Cb_PRE is
	port ( 
		D : in std_logic ;
		C : in std_logic ;
		CLR : in std_logic ;
		PRE : in std_logic ;
		Q : out std_logic );
end DFF_CLR_Cb_PRE ;

architecture Eval of DFF_CLR_Cb_PRE is
	
	signal synch_enable : std_logic ;
	
begin
	process ( C , CLR , PRE )
	begin
		if ( ( CLR = '1' ) and ( PRE = '1') ) then Q <= '0';
		elsif ( CLR = '1' ) then Q <= '0';
		elsif ( PRE = '1' ) then Q <= '1';
		elsif ( C'event and C = '0' ) then
			Q <= ( D );
		end if;
	end process;
	synch_enable <= ( '1' );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity TBUF is
	port ( 
		O : out std_logic ;
		I : in std_logic ;
		T : in std_logic );
end TBUF ;

architecture Eval of TBUF is
	
begin
	process ( I, T ) 
	begin
		if ( T = '0' ) then O <= ( I );
		else O <= 'Z';
		end if;
	end process;
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity AND2 is
	port ( 
		O : out std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end AND2 ;

architecture Eval of AND2 is
	
begin
	O <= ( I0 and I1 );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity OR2 is
	port ( 
		O : out std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end OR2 ;

architecture Eval of OR2 is
	
begin
	O <= not ( ( not I0 ) and ( not I1 ) );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity INV is
	port ( 
		O : out std_logic ;
		I : in std_logic );
end INV ;

architecture Eval of INV is
	
begin
	O <= ( ( not I ) );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity AND3 is
	port ( 
		O : out std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end AND3 ;

architecture Eval of AND3 is
	
begin
	O <= ( I0 and I1 and I2 );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity XOR2 is
	port ( 
		O : out std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end XOR2 ;

architecture Eval of XOR2 is
	
begin
	O <= ( I1 xor I0 );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity OR4 is
	port ( 
		O : out std_logic ;
		I3 : in std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end OR4 ;

architecture Eval of OR4 is
	
begin
	O <= not ( ( not I0 ) and ( not I1 ) and ( not I2 ) and ( not I3 ) 
	);
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity OR3 is
	port ( 
		O : out std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end OR3 ;

architecture Eval of OR3 is
	
begin
	O <= not ( ( not I0 ) and ( not I1 ) and ( not I2 ) );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity AND5 is
	port ( 
		O : out std_logic ;
		I4 : in std_logic ;
		I3 : in std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end AND5 ;

architecture Eval of AND5 is
	
begin
	O <= ( I0 and I1 and I2 and I3 and I4 );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity OR5 is
	port ( 
		O : out std_logic ;
		I4 : in std_logic ;
		I3 : in std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end OR5 ;

architecture Eval of OR5 is
	
begin
	O <= not ( ( not I0 ) and ( not I1 ) and ( not I2 ) and ( not I3 ) 
	and ( not I4 ) );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity AND4 is
	port ( 
		O : out std_logic ;
		I3 : in std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end AND4 ;

architecture Eval of AND4 is