📄 defeight.vhd
字号:
-- The octal D Flip flip module.
library ieee;
use ieee.std_logic_1164.all;
entity DFF8 is
port (D: in STD_LOGIC_VECTOR(0 to 7);
clk: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR(0 to 7));
end DFF8;
architecture DFF8 of DFF8 is
begin
process (clk)
begin
if (clk = '1' and clk'EVENT) then
Q <= D;
end if;
end process;
end DFF8;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -