enablecache.s

ARM嵌入式系统开发--软件设计与优化随书源代码。开发环境asm+c

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        AREA cache_routines , CODE, READONLY ; Start of Area block
     
        EXPORT enableMPU
        EXPORT enableCache
        EXPORT enableICache
        EXPORT enableDCache
        EXPORT disableCache
        EXPORT disableDCache
        EXPORT disableICache
        EXPORT enableRandom
        EXPORT enableRoundRobin

;------------------------------------
enableMPU
        MRC     p15,0,r0,c1,c0,0    ; Read control register
        ORR     r0,r0,#0x00000001   ; Enable MPU 
        MCR     p15,0,r0,c1,c0,0    ; Write to control register 1
        MOV     r0, #0
        MOV     pc, lr

;------------------------------------
disableCache
        MRC     p15,0,r0,c1,c0,0    ; Read control register
        BIC     r0,r0,#0x00001000   ; Clear Icache enable bit
        BIC     r0,r0,#0x00000004   ; Clear Dcache enable bit 
        MCR     p15,0,r0,c1,c0,0    ; Write to control register 1
        MOV     r0, #0
        MOV     pc,lr
;------------------------------------
disableDCache
        MRC     p15,0,r0,c1,c0,0    ; Read control register
        BIC     r0,r0,#0x00000004   ; Clear Dcache enable bit 
        MCR     p15,0,r0,c1,c0,0    ; Write to control register 1
        MOV     r0, #0
        MOV     pc,lr
;------------------------------------
disableICache
        MRC     p15,0,r0,c1,c0,0    ; Read control register
        BIC     r0,r0,#0x00001000   ; Clear Icache enable bit
        MCR     p15,0,r0,c1,c0,0    ; Write to control register 1
        MOV     r0, #0
        MOV     pc,lr
	
;------------------------------------
enableCache
        MRC     p15,0,r0,c1,c0,0    ; Read control register
        ORR     r0,r0,#0x00001000   ; Set enable Icache
        ORR     r0,r0,#0x00000004   ; Set enable Dcache and protection unit 
        MCR     p15,0,r0,c1,c0,0    ; Write to control register 1
        MOV     r0, #0
        MOV     pc, lr
        
;------------------------------------
enableICache
        MRC     p15,0,r0,c1,c0,0    ; Read control register
        ORR     r0,r0,#0x00001000   ; Enable Icache
        MCR     p15,0,r0,c1,c0,0    ; Write to control register 1
        MOV     r0, #0
        MOV     pc, lr

;------------------------------------
enableDCache
        MRC     p15,0,r0,c1,c0,0    ; Read control register
        ORR     r0,r0,#0x00000004   ; Enable Dcache 
        MCR     p15,0,r0,c1,c0,0    ; Write to control register 1
        MOV     r0, #0
        MOV     pc, lr

;------------------------------------
enableRoundRobin
        IF {CPU} = "ARM940T"
          MRC     p15,0,r0,c15,c0,0   ; Read round robin register
          ORR     r0,r0,#0x0000000c 	; enable d-cache round robin
          MCR     p15,0,r0,c15,c0,0   ; Write to test register c15
          MRC     p15,0,r0,c15,c0,0   ; Read round robin register
        ENDIF
        IF {CPU} = "ARM920T"       :LOR: \
           {CPU} = "ARM922T"
          MRC     p15,0,r0,c1,c0,0    ; Read control register
          ORR     r0,r0,#0x00004000   ; Enable Icache
          MCR     p15,0,r0,c1,c0,0    ; Write to control register 1
        ENDIF
;        MOV     r0, #0
        MOV     pc, lr
;------------------------------------
enableRandom
        IF {CPU} = "ARM940T"
          MRC     p15,0,r0,c15,c0,0   ; Read round robin register
          BIC     r0,r0,#0x0000000c 	; enable d-cache round robin
          MCR     p15,0,r0,c15,c0,0   ; Write to test register c15
          MRC     p15,0,r0,c15,c0,0   ; Read round robin register
        ENDIF
        IF {CPU} = "ARM920T"       :LOR: \
           {CPU} = "ARM922T"
          MRC     p15,0,r0,c1,c0,0    ; Read control register
          BIC     r0,r0,#0x00004000   ; Enable Icache
          MCR     p15,0,r0,c1,c0,0    ; Write to control register 1
        ENDIF
;        MOV     r0, #0
        MOV     pc, lr
;------------------------------------
        END