📄 nml67405x.h
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#define ILC_ILC28 0x07000000 /* IRQ28, IRQ29 */
#define ILC_ILC30 0x70000000 /* IRQ30, IRQ31 */
#define ILC_ILC32 0x00000007 /* IRQ32, IRQ33 */
#define ILC_ILC34 0x00000070 /* IRQ34, IRQ35 */
/*****************************************************/
/* interrupt number */
/*****************************************************/
#define INT_SYSTEM_TIMER 0
#define INT_WDT 1
#define INT_IVT 2
#define INT_GPIOA 4
#define INT_GPIOB 5
#define INT_GPIOC 6
#define INT_GPIOD 7
#define INT_SOFTIRQ 8
#define INT_UART0 9
#define INT_SIO0 10
#define INT_AD 11
#define INT_UART1 12
#define INT_SPI0 13
#define INT_TIMER0 16
#define INT_TIMER1 17
#define INT_TIMER2 18
#define INT_TIMER3 19
#define INT_TIMER4 20
#define INT_TIMER5 21
#define INT_DMA0 24
#define INT_DMA1 25
#define INT_GPIOE 28
#define INT_GPIOF 29
#define INT_EXINT1 34
#define INT_EXINT2 36
#define INT_EXINT3 38
#define INT_EXINT4 40
/****************************************************/
/* I2C control register */
/****************************************************/
#define I2C_BASE 0xB7800C00
#define I2CSADR (I2C_BASE+0x00) /* I2C slave address register */
#define I2CCTL (I2C_BASE+0x04) /* I2C control register */
#define I2CSR (I2C_BASE+0x08) /* I2C status register */
#define I2CDR (I2C_BASE+0x0C) /* I2C deta register */
#define I2CMON (I2C_BASE+0x10) /* I2C bus monitor register */
#define I2CBC (I2C_BASE+0x14) /* I2C bus trans speed set counter */
/* bit field of I2CCTL register */
#define I2CCTL_I2CMD 0x00000003
#define I2CCTL_I2CRSTA 0x00000004
#define I2CCTL_I2CTXAK 0x00000008
#define I2CCTL_I2CMTX 0x00000010
#define I2CCTL_I2CMSTA 0x00000020
#define I2CCTL_I2CAASIE 0x00000040
#define I2CCTL_I2CMEN 0x00000080
#define I2CCTL_I2CALIE 0x00000100
#define I2CCTL_I2CCFIE 0x00000200
#define I2CCTL_I2CSTPIE 0x00000800
#define I2CCTL_I2CDR_LDEN 0x00001000
#define I2CCTL_I2CCS 0x00002000
/* bit field of I2CSR register */
#define I2CSR_I2CRXAK 0x00000001
#define I2CSR_I2CMIF 0x00000002
#define I2CSR_I2CSRW 0x00000004
#define I2CSR_I2CDR_LD 0x00000008
#define I2CSR_I2CMAL 0x00000010
#define I2CSR_I2CMBB 0x00000020
#define I2CSR_I2CMAAS 0x00000040
#define I2CSR_I2CMCF 0x00000080
#define I2CSR_I2CSTP 0x00000200
/****************************************************/
/* I2S control register */
/****************************************************/
#define I2S_BASE 0xB7900000
#define I2SFIFOO (I2S_BASE+0x00) /* I2S FIFO Output register */
#define I2SCONO (I2S_BASE+0x04) /* I2S control output */
#define I2SCLKO (I2S_BASE+0x08) /* I2S clk control output */
#define I2SAFRO (I2S_BASE+0x0C) /* I2S almost full register output */
#define I2SAERO (I2S_BASE+0x10) /* I2S almost empty register output */
#define I2SIMRO (I2S_BASE+0x14) /* I2S interrupt mask register output */
#define I2SISTO (I2S_BASE+0x18) /* I2S interrupt status register output */
#define I2SLRSO (I2S_BASE+0x1C) /* I2S left/right status & FIFO level register output */
#define I2SFIFOI (I2S_BASE+0x20) /* I2S FIFO input register */
#define I2SCONI (I2S_BASE+0x24) /* I2S control input */
#define I2SCLKI (I2S_BASE+0x28) /* I2S clk control input */
#define I2SAFRI (I2S_BASE+0x2C) /* I2S almost full register input */
#define I2SAERI (I2S_BASE+0x30) /* I2S almost empty register input */
#define I2SIMRI (I2S_BASE+0x34) /* I2S interrupt mask register input */
#define I2SISTI (I2S_BASE+0x38) /* I2S interrupt status register input */
#define I2SLRSI (I2S_BASE+0x3C) /* I2S left/right status & FIFO level register input */
/* bit field of I2SCONO register */
#define I2SCONO_TSET_ISSFSO 0x00000003
#define I2SCONO_TSET_ISMSB 0x00000004
#define I2SCONO_TSET_ISWSL 0x00000008
#define I2SCONO_TSET_ISDLY 0x00000010
#define I2SCONO_TSET_ISRUN 0x00000020
#define I2SCONO_TSET_ISSFO 0x000000C0
#define I2SCONO_TSET_ISSCKF 0x00000100
#define I2SCONO_TSET_ISBIT 0x00000600
#define I2SCONO_TSET_AFO 0x00001800
#define I2SCONO_TSET_STOP 0x00002000
/* bit field of I2SCONI register */
#define I2SCONI_RSET_ISSFSO 0x00000003
#define I2SCONI_RSET_ISMSB 0x00000004
#define I2SCONI_RSET_ISWSL 0x00000008
#define I2SCONI_RSET_ISDLY 0x00000010
#define I2SCONI_RSET_ISRUN 0x00000020
#define I2SCONI_RSET_ISSFO 0x000000C0
#define I2SCONI_RSET_ISSCKF 0x00000100
#define I2SCONI_RSET_ISBIT 0x00000600
#define I2SCONI_RSET_AFO 0x00001800
#define I2SCONI_RSET_STOP 0x00002000
/* bit field of I2SCLKO register */
#define I2SCLKO_TSET_ISCLR 0x00000001
#define I2SCLKO_TSET_ISMST 0x00000004
/* bit field of I2SCLKI register */
#define I2SCLKI_RSET_ISCLR 0x00000001
#define I2SCLKI_RSET_ISMST 0x00000004
/* bit field of I2SLRSO register */
#define I2SLRSO_TMON_LR 0x00000001
#define I2SLRSO_TFIFOLVL 0x0001FF00
/* bit field of I2SLRSI register */
#define I2SLRSI_RMON_LR 0x00000001
#define I2SLRSI_RFIFOLVL 0x0001FF00
/****************************************************/
/* SPI control register */
/****************************************************/
#define SPI0_BASE 0xB7B02000
#define SPCR0 (SPI0_BASE+0x00) /* SPI control register 0 */
#define SPBRR0 (SPI0_BASE+0x04) /* SPI baudrate register 0 */
#define SPSR0 (SPI0_BASE+0x08) /* SPI status register 0 */
#define SPDWR0 (SPI0_BASE+0x0C) /* SPI write data register 0 */
#define SPDRR0 (SPI0_BASE+0x10) /* SPI read data register 0 */
#define TEST0 (SPI0_BASE+0x14) /* for test 0 */
/* bit field of SPCR0 register */
#define SPCR0_SPE 0x00000001
#define SPCR0_MSTR 0x00000002
#define SPCR0_MODFEN 0x00000008
#define SPCR0_LSBF 0x00000010
#define SPCR0_CPHA 0x00000020
#define SPCR0_CPOL 0x00000040
#define SPCR0_TFIE 0x00000100
#define SPCR0_RFIE 0x00000200
#define SPCR0_FIE 0x00000400
#define SPCR0_ORIE 0x00000800
#define SPCR0_MDFIE 0x00001000
#define SPCR0_TFIC 0x000F0000
#define SPCR0_RFIC 0x00F00000
#define SPCR0_FICLR 0x01000000
#define SPCR0_SSZ 0x02000000
#define SPCR0_SOZ 0x04000000
#define SPCR0_MOZ 0x08000000
/* bit field of SPSR0 register */
#define SPSR0_TFI 0x00000001
#define SPSR0_RFI 0x00000002
#define SPSR0_FI 0x00000004
#define SPSR0_ORF 0x00000008
#define SPSR0_MDF 0x00000010
#define SPSR0_SPIF 0x00000020
#define SPSR0_TFD 0x000007C0
#define SPSR0_RFD 0x0000F800
#define SPSR0_WOF 0x00010000
#define SPSR0_TFF 0x00020000
#define SPSR0_TFE 0x00040000
#define SPSR0_RFF 0x00080000
#define SPSR0_RFE 0x00100000
/* bit field of SPBRR0 register */
#define SPBRR0_SPBR 0x000003FF
#define SPBRR0_SIZE 0x00000400
#define SPBRR0_LEAD 0x00003000
#define SPBRR0_LAG 0x0000C000
#define SPBRR0_DTL 0x01FF0000
#define SPI1_BASE 0xB7B03000
#define SPCR1 (SPI1_BASE+0x00) /* SPI control register 1 */
#define SPBRR1 (SPI1_BASE+0x04) /* SPI baudrate register 1 */
#define SPSR1 (SPI1_BASE+0x08) /* SPI status register 1 */
#define SPDWR1 (SPI1_BASE+0x0C) /* SPI write data register 1 */
#define SPDRR1 (SPI1_BASE+0x10) /* SPI read data register 1 */
#define TEST1 (SPI1_BASE+0x14) /* for test 1 */
/* bit field of SPCR1 register */
#define SPCR1_SPE 0x00000001
#define SPCR1_MSTR 0x00000002
#define SPCR1_MODFEN 0x00000008
#define SPCR1_LSBF 0x00000010
#define SPCR1_CPHA 0x00000020
#define SPCR1_CPOL 0x00000040
#define SPCR1_TFIE 0x00000100
#define SPCR1_RFIE 0x00000200
#define SPCR1_FIE 0x00000400
#define SPCR1_ORIE 0x00000800
#define SPCR1_MDFIE 0x00001000
#define SPCR1_TFIC 0x000F0000
#define SPCR1_RFIC 0x00F00000
#define SPCR1_FICLR 0x01000000
#define SPCR1_SSZ 0x02000000
#define SPCR1_SOZ 0x04000000
#define SPCR1_MOZ 0x08000000
/* bit field of SPSR0 register */
#define SPSR1_TFI 0x00000001
#define SPSR1_RFI 0x00000002
#define SPSR1_FI 0x00000004
#define SPSR1_ORF 0x00000008
#define SPSR1_MDF 0x00000010
#define SPSR1_SPIF 0x00000020
#define SPSR1_TFD 0x000007C0
#define SPSR1_RFD 0x0000F800
#define SPSR1_WOF 0x00010000
#define SPSR1_TFF 0x00020000
#define SPSR1_TFE 0x00040000
#define SPSR1_RFF 0x00080000
#define SPSR1_RFE 0x00100000
/* bit field of SPBRR1 register */
#define SPBRR1_SPBR 0x000003FF
#define SPBRR1_SIZE 0x00000400
#define SPBRR1_LEAD 0x00003000
#define SPBRR1_LAG 0x0000C000
#define SPBRR1_DTL 0x01FF0000
/****************************************************/
/* RTC control register */
/****************************************************/
#define RTC_BASE 0xB7C00000
#define S1 (RTC_BASE+0x00) /* 1 second register */
#define S10 (RTC_BASE+0x04) /* 10 second register */
#define M1 (RTC_BASE+0x08) /* 1 minute register */
#define M10 (RTC_BASE+0x0C) /* 10 minute register */
#define H1 (RTC_BASE+0x10) /* 1 hour register */
#define H10 (RTC_BASE+0x14) /* 10 hour register */
#define D1 (RTC_BASE+0x18) /* 1 day register */
#define D10 (RTC_BASE+0x1C) /* 10 day register */
#define MO1 (RTC_BASE+0x20) /* 1 month register */
#define MO10 (RTC_BASE+0x24) /* 10 month register */
#define Y1 (RTC_BASE+0x28) /* 1 year register */
#define Y10 (RTC_BASE+0x2C) /* 10 yaer register */
#define W (RTC_BASE+0x30) /* week register */
#define CD (RTC_BASE+0x34) /* control register D */
#define CE (RTC_BASE+0x38) /* control register E */
#define CF (RTC_BASE+0x3C) /* control register F */
/* bit field of CF register */
#define CF_RESET_ON 0x01
#define CF_STOP_ON 0x02
#define CF_TEST 0x00
#ifdef __cplusplus
}; /* End of 'extern "C"' */
#endif
#endif /* End of ML674061.h */
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