nml67405x.h

uCos_II到ARM7的移植

#define PCR_BASE8	0xB7A08000  	/* base address */
#define PO8			(PCR_BASE8+0x00) 	/* port8(PI) output register */
#define PI8			(PCR_BASE8+0x04) 	/* port8(PI) input register */
#define PM8			(PCR_BASE8+0x08) 	/* port8(PI) Mode register */
#define IE8			(PCR_BASE8+0x0C) 	/* port8(PI) interrupt enable */
#define IM8			(PCR_BASE8+0x10) 	/* port8(PI) interrupt Mode register */
#define IS8			(PCR_BASE8+0x18) 	/* port8(PI) interrupt Status register*/

#define PCR_BASE9	0xB7A09000  	/* base address */
#define PO9			(PCR_BASE9+0x00) 	/* port9(PJ) output register */
#define PI9			(PCR_BASE9+0x04) 	/* port9(PJ) input register */
#define PM9			(PCR_BASE9+0x08) 	/* port9(PJ) Mode register */
#define IE9			(PCR_BASE9+0x0C) 	/* port9(PJ) interrupt enable */
#define IM9			(PCR_BASE9+0x10) 	/* port9(PJ) interrupt Mode register */
#define IS9			(PCR_BASE9+0x18) 	/* port9(PJ) interrupt Status register*/

#define PCR_BASE10	0xB7A0A000  	/* base address */
#define PO10		(PCR_BASE10+0x00) 	/* port10(PK) output register */
#define PI10		(PCR_BASE10+0x04) 	/* port10(PK) input register */
#define PM10		(PCR_BASE10+0x08) 	/* port10(PK) Mode register */
#define IE10		(PCR_BASE10+0x0C) 	/* port10(PK) interrupt enable */
#define IM10		(PCR_BASE10+0x10) 	/* port10(PK) interrupt Mode register */
#define IS10		(PCR_BASE10+0x18) 	/* port10(PK) interrupt Status register*/

#define PCR_BASE11	0xB7A0B000  	/* base address */
#define PO11		(PCR_BASE11+0x00) 	/* port11(PL) output register */
#define PI11		(PCR_BASE11+0x04) 	/* port11(PL) input register */
#define PM11		(PCR_BASE11+0x08) 	/* port11(PL) Mode register */
#define IE11		(PCR_BASE11+0x0C) 	/* port11(PL) interrupt enable */
#define IM11		(PCR_BASE11+0x10) 	/* port11(PL) interrupt Mode register */
#define IS11		(PCR_BASE11+0x18) 	/* port11(PL) interrupt Status register*/

#define PCR_BASE12	0xB7A0C000  	/* base address */
#define PO12		(PCR_BASE12+0x00) 	/* port12(PM) output register */
#define PI12		(PCR_BASE12+0x04) 	/* port12(PM) input register */
#define PM12		(PCR_BASE12+0x08) 	/* port12(PM) Mode register */
#define IE12		(PCR_BASE12+0x0C) 	/* port12(PM) interrupt enable */
#define IM12		(PCR_BASE12+0x10) 	/* port12(PM) interrupt Mode register */
#define IS12		(PCR_BASE12+0x18) 	/* port12(PM) interrupt Status register*/

#define PCR_BASE13	0xB7A0D000  	/* base address */
#define PO13		(PCR_BASE13+0x00) 	/* port13(PN) output register */
#define PI13		(PCR_BASE13+0x04) 	/* port13(PN) input register */
#define PM13		(PCR_BASE13+0x08) 	/* port13(PN) Mode register */
#define IE13		(PCR_BASE13+0x0C) 	/* port13(PN) interrupt enable */
#define IM13		(PCR_BASE13+0x10) 	/* port13(PN) interrupt Mode register */
#define IS13		(PCR_BASE13+0x18) 	/* port13(PN) interrupt Status register*/

#define PCR_BASE14	0xB7A0E000  	/* base address */
#define PO14		(PCR_BASE14+0x00) 	/* port14(PO) output register */
#define PI14		(PCR_BASE14+0x04) 	/* port14(PO) input register */
#define PM14		(PCR_BASE14+0x08) 	/* port14(PO) Mode register */
#define IE14		(PCR_BASE14+0x0C) 	/* port14(PO) interrupt enable */
#define IM14		(PCR_BASE14+0x10) 	/* port14(PO) interrupt Mode register */
#define IS14		(PCR_BASE14+0x18) 	/* port14(PO) interrupt Status register*/

/*****************************************************/
/*    ADC control register                           */
/*****************************************************/
#define ADC_BASE    0xB6000000  /* base address */
#define ADCON0      (ADC_BASE+0x00) /* ADC control 0 register */
#define ADCON1      (ADC_BASE+0x04) /* ADC control 1 register */
#define ADCON2      (ADC_BASE+0x08) /* ADC control 2 register */
#define ADINT       (ADC_BASE+0x0C) /* AD interrupt control register */
#define ADFINT      (ADC_BASE+0x10) /* AD Forced interrupt register */
#define ADR0        (ADC_BASE+0x14) /* AD Result 0 register */
#define ADR1        (ADC_BASE+0x18) /* AD Result 1 register */
#define ADR2        (ADC_BASE+0x1C) /* AD Result 2 register */
#define ADR3        (ADC_BASE+0x20) /* AD Result 3 register */


/* bit field of ADCON0 register */
#define ADCON0_CH0_3    0x0000  /* CH0-CH3 */
#define ADCON0_CH1_3    0x0001  /* CH1-CH3 */
#define ADCON0_CH2_3    0x0002  /* CH2-CH3 */
#define ADCON0_CH3	    0x0003  /* CH3 */
#define ADCON0_ADRUN    0x0010  /* AD conversion start */
#define ADCON0_SCNC     0x0040  /* Stop after a round */

/* bit field of ADCON1 register */
#define ADCON1_CH0      0x0000  /* CH0 */
#define ADCON1_CH1      0x0001  /* CH1 */
#define ADCON1_CH2      0x0002  /* CH2 */
#define ADCON1_CH3      0x0003  /* CH3 */
#define ADCON1_STS      0x0010  /* AD conversion start */

/* bit field of ADCON2 register */
#define ADCON2_CLK2     0x0000  /* CPUCLK/2 */
#define ADCON2_CLK4     0x0001  /* CPUCLK/4 */
#define ADCON2_CLK8     0x0002  /* CPUCLK/8 */
#define ADCON2_CLK16    0x0003  /* CPUCLK/16 */
#define ADCON2_CLK32    0x0004  /* CPUCLK/32 */
#define ADCON2_CLK64    0x0005  /* CPUCLK/64 */

/* bit field of ADINT register */
#define ADINT_INTSN     0x0001  /* AD conversion of ch7 finished (scan mode) */
#define ADINT_INTST     0x0002  /* AD conversion finished (select mode) */
#define ADINT_ADSNIE    0x0004  /* enable interrupt (scan mode) */
#define ADINT_ADSTIE    0x0008  /* enable interrupt (select mode) */

/* bit field of ADFINT register */
#define ADFINT_ADFAS    0x0001  /* Assert interrupt signal */

/*****************************************************/
/*    DMA control register                           */
/*****************************************************/
#define DMA_BASE    0x7BE00000  /* base address */
#define DMAMOD      (DMA_BASE+0x0000)   /* DMA Mode register */
#define DMASTA      (DMA_BASE+0x0004)   /* DMA Status register */
#define DMAINT      (DMA_BASE+0x0008)   /* DMA interrupt Status register */
#define DMACMSK0    (DMA_BASE+0x0100)   /* Channel 0 Mask register */
#define DMACTMOD0   (DMA_BASE+0x0104)   /* Channel 0 Transfer Mode register */
#define DMACSAD0    (DMA_BASE+0x0108)   /* Channel 0 Source Address register */
#define DMACDAD0    (DMA_BASE+0x010C)   /* Channel 0 Destination Address register */
#define DMACSIZ0    (DMA_BASE+0x0110)   /* Channel 0 Transfer Size register */
#define DMACCINT0   (DMA_BASE+0x0114)   /* Channel 0 interrupt Clear register */
#define DMACMSK1    (DMA_BASE+0x0200)   /* Channel 1 Mask register */
#define DMACTMOD1   (DMA_BASE+0x0204)   /* Channel 1 Transfer Mode register */
#define DMACSAD1    (DMA_BASE+0x0208)   /* Channel 1 Source Address register */
#define DMACDAD1    (DMA_BASE+0x020C)   /* Channel 1 Destination Address register */
#define DMACSIZ1    (DMA_BASE+0x0210)   /* Channel 1 Transfer Size register */
#define DMACCINT1   (DMA_BASE+0x0214)   /* Channel 1 interrupt Clear register */

/* bit field of DMAMOD register */
#define DMAMOD_FIX  0x0000  /* Priority of DMA channel : CH0 > CH1 */
#define DMAMOD_RR   0x0001  /* Priority of DMA channel : Round robin */

/* bit field of DMASTA register */
#define DMASTA_STA0 0x0001  /* Non-transmitted data is in CH0 */
#define DMASTA_STA1 0x0002  /* Non-transmitted data is in CH1 */

/* bit field of DMAINT register */
#define DMAINT_IREQ0    0x00000001  /* CH0 interrupt */
#define DMAINT_IREQ1    0x00000002  /* CH1 interrupt */
#define DMAINT_ISTA0    0x00000100  /* CH0 abnormal end */
#define DMAINT_ISTA1    0x00000200  /* CH1 abnormal end */
#define DMAINT_ISTP0    0x00010000  /* CH0 abnormal end situation */
#define DMAINT_ISTP1    0x00020000  /* CH1 abnormal end situation */

/* bit field of DMAMSK0,1 register */
#define DMACMSK_MSK  0x00000001  /* Mask */

/* bit field of DMATMOD0,1 register */
#define DMACTMOD_ARQ    0x00000001  /* Auto request */
#define DMACTMOD_ERQ    0x00000000  /* External request */
#define DMACTMOD_BYTE   0x00000000  /* Byte transmission */
#define DMACTMOD_HWORD  0x00000002  /* Half word transmission */
#define DMACTMOD_WORD   0x00000004  /* Word transmission */
#define DMACTMOD_SFA    0x00000000  /* Source data type(fixed address device) */
#define DMACTMOD_SIA    0x00000008  /* Source data type(incremental address device) */
#define DMACTMOD_DFA    0x00000000  /* Destination data type(fixed address device) */
#define DMACTMOD_DIA    0x00000010  /* Destination data type(incremental address device) */
#define DMACTMOD_BM     0x00000000  /* Bus request mode(burst mode) */
#define DMACTMOD_CSM    0x00000020  /* Bus request mode(cycle steal mode) */
#define DMACTMOD_IMK    0x00000040  /* interrupt mask */


/*****************************************************/
/*    extended interrupt control register                     */
/*****************************************************/
#define EIC_BASE	0x7BF00000  /* base address */
#define EXIRS		(EIC_BASE+0x00) /* Extended interrupt Size register */
#define EXIRCL		(EIC_BASE+0x04) /* Extended interrupt Clear register */
#define EXIRQA		(EIC_BASE+0x10)	/* Extended IRQ register A */
#define EXIRQB		(EIC_BASE+0x20)	/* Extended IRQ register B */
#define EXIRQC		(EIC_BASE+0x30)	/* Extended IRQ register C */
#define EXILCA		(EIC_BASE+0x18)	/* Extended IRQ Level contorol register A */
#define EXILCB		(EIC_BASE+0x28)	/* Extended IRQ Level contorol register B */
#define EXILCC		(EIC_BASE+0x38)	/* Extended IRQ Level contorol register C */
#define EXIDMA		(EIC_BASE+0x24)	/* Extended IRQ edge mode set register */
#define EXIRQSA		(EIC_BASE+0x1C)	/* Extended interrupt IRQ status register A */
#define EXIRQSB		(EIC_BASE+0x2C)	/* Extended interrupt IRQ status register B */
#define EXFIQ		(EIC_BASE+0x80)	/* Extended FIQ register */
#define EXFIDM		(EIC_BASE+0x84)	/* Extended FIQ mode register */

/* bit field of IRQA register */
#define IRQA_IRQ16  0x00000001  /* IRQ16 */
#define IRQA_IRQ17  0x00000002  /* IRQ17 */
#define IRQA_IRQ18  0x00000004  /* IRQ18 */
#define IRQA_IRQ19  0x00000008  /* IRQ19 */
#define IRQA_IRQ20  0x00000010  /* IRQ20 */
#define IRQA_IRQ21  0x00000020  /* IRQ21 */
#define IRQA_IRQ22  0x00000040  /* IRQ22 */
#define IRQA_IRQ23  0x00000080  /* IRQ23 */
#define IRQA_IRQ24  0x00000100  /* IRQ24 */
#define IRQA_IRQ25  0x00000200  /* IRQ25 */
#define IRQA_IRQ26  0x00000400  /* IRQ26 */
#define IRQA_IRQ27  0x00000800  /* IRQ27 */
#define IRQA_IRQ28  0x00001000  /* IRQ28 */
#define IRQA_IRQ29  0x00002000  /* IRQ29 */
#define IRQA_IRQ30  0x00004000  /* IRQ30 */
#define IRQA_IRQ31  0x00008000  /* IRQ31 */

#define IRQB_IRQ32  0x00000001  /* IRQ32 */
#define IRQB_IRQ33  0x00000002  /* IRQ33 */
#define IRQB_IRQ34  0x00000004  /* IRQ34 */
#define IRQB_IRQ35  0x00000008  /* IRQ35 */
#define IRQB_IRQ36  0x00000010  /* IRQ36 */
#define IRQB_IRQ37  0x00000020  /* IRQ37 */
#define IRQB_IRQ38  0x00000040  /* IRQ38 */
#define IRQB_IRQ39  0x00000080  /* IRQ39 */
#define IRQB_IRQ40  0x00000100  /* IRQ40 */
#define IRQB_IRQ41  0x00000200  /* IRQ41 */
#define IRQB_IRQ42  0x00000400  /* IRQ42 */
#define IRQB_IRQ43  0x00000800  /* IRQ43 */
#define IRQB_IRQ44  0x00001000  /* IRQ44 */
#define IRQB_IRQ45  0x00002000  /* IRQ45 */
#define IRQB_IRQ46  0x00004000  /* IRQ46 */
#define IRQB_IRQ47  0x00008000  /* IRQ47 */

#define IRQC_IRQ48  0x00000001  /* IRQ48 */
#define IRQC_IRQ49  0x00000002  /* IRQ49 */
#define IRQC_IRQ50  0x00000004  /* IRQ50 */
#define IRQC_IRQ51  0x00000008  /* IRQ51 */
#define IRQC_IRQ52  0x00000010  /* IRQ52 */
#define IRQC_IRQ53  0x00000020  /* IRQ53 */
#define IRQC_IRQ54  0x00000040  /* IRQ54 */
#define IRQC_IRQ55  0x00000080  /* IRQ55 */
#define IRQC_IRQ56  0x00000100  /* IRQ56 */
#define IRQC_IRQ57  0x00000200  /* IRQ57 */
#define IRQC_IRQ58  0x00000400  /* IRQ58 */
#define IRQC_IRQ59  0x00000800  /* IRQ59 */
#define IRQC_IRQ60  0x00001000  /* IRQ60 */
#define IRQC_IRQ61  0x00002000  /* IRQ61 */
#define IRQC_IRQ62  0x00004000  /* IRQ62 */
#define IRQC_IRQ63  0x00008000  /* IRQ63 */

/* bit field of IDM register */
#define IDM_INT_L_L 0x00000000  /* level sensing, interrupt occurs when 'L' */
#define IDM_INT_L_H 0x0000AAAA  /* level sensing, interrupt occurs when 'H' */
#define IDM_INT_E_F 0x00005555  /* edge sensing, interrupt occurs when falling edge */
#define IDM_INT_E_R 0x0000FFFF  /* edge sensing, interrupt occurs when rising edge */

#define IDM_IDM34   0x00000004  /* IRQ34, IRQ35 */
#define IDM_IDM36   0x00000010  /* IRQ36, IRQ37 */
#define IDM_IDM38   0x00000040  /* IRQ38, IRQ39 */
#define IDM_IDM40   0x00000100  /* IRQ40, IRQ41 */
#define IDM_IDM42   0x00000400  /* IRQ42, IRQ43 */
#define IDM_IDMP34  0x00000008  /* IRQ34, IRQ35 */
#define IDM_IDMP36  0x00000020  /* IRQ36, IRQ37 */
#define IDM_IDMP38  0x00000080  /* IRQ38, IRQ39 */
#define IDM_IDMP40  0x00000200  /* IRQ40, IRQ41 */
#define IDM_IDMP42  0x00000800  /* IRQ42, IRQ43 */

#define IDM_IRQ33   0x00000003	/* IRQ33 */
#define IDM_IRQ34   0x0000000C	/* IRQ34 */
#define IDM_IRQ35   0x0000000C	/* IRQ35 */
#define IDM_IRQ36   0x00000030	/* IRQ36 */
#define IDM_IRQ37   0x00000030	/* IRQ37 */
#define IDM_IRQ38   0x000000C0	/* IRQ38 */
#define IDM_IRQ39   0x000000C0	/* IRQ39 */
#define IDM_IRQ40   0x00000300	/* IRQ40 */
#define IDM_IRQ41   0x00000300	/* IRQ41 */
#define IDM_IRQ42   0x00000C00	/* IRQ42 */
#define IDM_IRQ43   0x00000C00	/* IRQ43 */

/* bit field of EXILC register */
#define ILC_INT_LV1 0x11111111  /* interrupt level 1 */
#define ILC_INT_LV2 0x22222222  /* interrupt level 2 */
#define ILC_INT_LV3 0x33333333  /* interrupt level 3 */
#define ILC_INT_LV4 0x44444444  /* interrupt level 4 */
#define ILC_INT_LV5 0x55555555  /* interrupt level 5 */
#define ILC_INT_LV6 0x66666666  /* interrupt level 6 */
#define ILC_INT_LV7 0x77777777  /* interrupt level 7 */
#define ILC_ILC16   0x00000007  /* IRQ16, IRQ17 */
#define ILC_ILC18   0x00000070  /* IRQ18, IRQ19 */
#define ILC_ILC20   0x00000700  /* IRQ20, IRQ21 */
#define ILC_ILC22   0x00007000  /* IRQ22, IRQ23 */
#define ILC_ILC24   0x00070000  /* IRQ24, IRQ25 */
#define ILC_ILC26   0x00700000  /* IRQ26, IRQ27 */