nml67405x.h

uCos_II到ARM7的移植

#define FTM2IOLV	(FTM_BASE+0x54)	/* timer2 I/O level register */
#define FTM2OUT		(FTM_BASE+0x58)	/* timer2 out register */
#define FTM2IER		(FTM_BASE+0x5C) /* timer2 interrupt enable register */
#define FTM3CON		(FTM_BASE+0x60) /* timer3 control register */
#define FTM3ST		(FTM_BASE+0x64)	/* timer3 status register */
#define FTM3C		(FTM_BASE+0x68) /* timer3 counter register */
#define FTM3R		(FTM_BASE+0x6C)	/* timer3 register */
#define FTM3GR		(FTM_BASE+0x70)	/* timer3 wide use register */
#define FTM3IOLV	(FTM_BASE+0x74)	/* timer3 I/O level register */
#define FTM3OUT		(FTM_BASE+0x78)	/* timer3 out register */
#define FTM3IER		(FTM_BASE+0x7C) /* timer3 interrupt enable register */
#define FTM4CON		(FTM_BASE+0x80) /* timer4 control register */
#define FTM4ST		(FTM_BASE+0x84)	/* timer4 status register */
#define FTM4C		(FTM_BASE+0x88) /* timer4 counter register */
#define FTM4R		(FTM_BASE+0x8C)	/* timer4 register */
#define FTM4GR		(FTM_BASE+0x90)	/* timer4 wide use register */
#define FTM4IOLV	(FTM_BASE+0x94)	/* timer4 I/O level register */
#define FTM4OUT		(FTM_BASE+0x98)	/* timer4 out register */
#define FTM4IER		(FTM_BASE+0x9C) /* timer4 interrupt enable register */
#define FTM5CON		(FTM_BASE+0xA0) /* timer5 control register */
#define FTM5ST		(FTM_BASE+0xA4)	/* timer5 status register */
#define FTM5C		(FTM_BASE+0xA8) /* timer5 counter register */
#define FTM5R		(FTM_BASE+0xAC)	/* timer5 register */
#define FTM5GR		(FTM_BASE+0xB0)	/* timer5 wide use register */
#define FTM5IOLV	(FTM_BASE+0xB4)	/* timer5 I/O level register */
#define FTM5OUT		(FTM_BASE+0xB8)	/* timer5 out register */
#define FTM5IER		(FTM_BASE+0xBC) /* timer5 interrupt enable register */
#define	FTMEN		(FTM_BASE+0xC0)	/* timer enable register */
#define FTMDIS		(FTM_BASE+0xC4)	/* timer disable register */

/* bit field of FTMnCON */
#define FTM0CON_FTMCLK	0x07
#define FTM1CON_FTMCLK	0x07
#define FTM2CON_FTMCLK	0x07
#define FTM3CON_FTMCLK	0x07
#define FTM4CON_FTMCLK	0x07
#define FTM5CON_FTMCLK	0x07

#define FTM0CON_MOD		0x18
#define FTM1CON_MOD		0x18
#define FTM2CON_MOD		0x18
#define FTM3CON_MOD		0x18
#define FTM4CON_MOD		0x18
#define FTM5CON_MOD		0x18

/* bit field of FTMnST */
#define FTM0ST_CM_CAPEV	0x1
#define FTM1ST_CM_CAPEV	0x1
#define FTM2ST_CM_CAPEV	0x1
#define FTM3ST_CM_CAPEV	0x1
#define FTM4ST_CM_CAPEV	0x1
#define FTM5ST_CM_CAPEV	0x1

#define FTM0ST_OVF		0x2
#define FTM1ST_OVF		0x2
#define FTM2ST_OVF		0x2
#define FTM3ST_OVF		0x2
#define FTM4ST_OVF		0x2
#define FTM5ST_OVF		0x2

/* bit field of FTMnIER */
#define FTM0IER_OVFIE	0x2
#define FTM1IER_OVFIE	0x2
#define FTM2IER_OVFIE	0x2
#define FTM3IER_OVFIE	0x2
#define FTM4IER_OVFIE	0x2
#define FTM5IER_OVFIE	0x2

/* bit field of FTMDIS */
#define FTMDIS_FTMDIS0	0x01	/* TIMER0 */
#define FTMDIS_FTMDIS1	0x02	/* TIMER1 */
#define FTMDIS_FTMDIS2	0x04	/* TIMER2 */
#define FTMDIS_FTMDIS3	0x08	/* TIMER3 */
#define FTMDIS_FTMDIS4	0x10	/* TIMER4 */
#define FTMDIS_FTMDIS5	0x20	/* TIMER5 */

/*****************************************************/
/*    Watch Dog Timer control register               */
/*****************************************************/
#define WDT_BASE    0xB7E00000  /* base address */
#define WDTCON      (WDT_BASE+0x00) /* Watch Dog Timer control register */
#define TBGCON     	(WDT_BASE+0x04) /* time base counter control register */
#define INTST		(WDT_BASE+0x08)	/* interrupt status register */
#define OVFAST		(WDT_BASE+0x0C)	/* WDTOVFN assert register */
#define WDTCNT		(WDT_BASE+0x10)	/* WDT counter register */

/* bit field of WDTCON */
#define WDTCON_0xC3 0xC3    /* 0xC3 */
#define WDTCON_0x3C 0x3C    /* 0x3C */

/* bit field of TBGCON */
#define TBGCON_WDHLT	0x80	/* HALT */
#define TBGCON_OFINT	0x40	/* reset by overflow */
#define TBGCON_WDCK32	0x00	/* APB_CLK/32 */
#define TBGCON_WDCK64	0x01	/* APB_CLK/64 */
#define TBGCON_WDCK128	0x02	/* APB_CLK/128 */
#define TBGCON_WDCK256	0x03	/* APB_CLK/256 */
#define TBGCON_WDCK512	0x04	/* APB_CLK/512 */
#define TBGCON_WDCK1024	0x05	/* APB_CLK/1024 */
#define TBGCON_WDCK2048	0x06	/* APB_CLK/2048 */
#define TBGCON_WDCK4096	0x07	/* APB_CLK/4096 */
#define TBGCON_0x5A		0x5A

/* bit field of INTST */
#define INTST_RSTSTATUS 0x01
#define INTST_WDTINT    0x10

/*****************************************************/
/*    UART control register                          */
/*****************************************************/
#define UCR_BASE     0xB7B00000  /* base address */
#define UARTRBR0     (UCR_BASE+0x00) /* receiver buffer register */
#define UARTTHR0     (UCR_BASE+0x00) /* transmitter buffer register */
#define UARTIER0     (UCR_BASE+0x04) /* interrupt enable register */
#define UARTIIR0     (UCR_BASE+0x08) /* interrupt identification */
#define UARTFCR0     (UCR_BASE+0x08) /* FIFO control register */
#define UARTLCR0     (UCR_BASE+0x0C) /* line control register */
#define UARTMCR0     (UCR_BASE+0x10) /* modem control register */
#define UARTLSR0     (UCR_BASE+0x14) /* line status register */
#define UARTMSR0     (UCR_BASE+0x18) /* modem status register */
#define UARTSCR0     (UCR_BASE+0x1C) /* scratchpad register */
#define UARTDLL0     (UCR_BASE+0x00) /* divisor latch(LSB) */
#define UARTDLM0     (UCR_BASE+0x04) /* divisor latch(MSB) */

#define UCR_BASE1    0xB7B01000  /* base address */
#define UARTRBR1     (UCR_BASE1+0x00) /* receiver buffer register */
#define UARTTHR1     (UCR_BASE1+0x00) /* transmitter buffer register */
#define UARTIER1     (UCR_BASE1+0x04) /* interrupt enable register */
#define UARTIIR1     (UCR_BASE1+0x08) /* interrupt identification */
#define UARTFCR1     (UCR_BASE1+0x08) /* FIFO control register */
#define UARTLCR1     (UCR_BASE1+0x0C) /* line control register */
#define UARTMCR1     (UCR_BASE1+0x10) /* modem control register */
#define UARTLSR1     (UCR_BASE1+0x14) /* line status register */
#define UARTMSR1     (UCR_BASE1+0x18) /* modem status register */
#define UARTSCR1     (UCR_BASE1+0x1C) /* scratchpad register */
#define UARTDLL1     (UCR_BASE1+0x00) /* divisor latch(LSB) */
#define UARTDLM1     (UCR_BASE1+0x04) /* divisor latch(MSB) */

/* bit field of UARTLCR register */
#define UARTLCR_LEN5    0x0000  /* data length : 5bit */
#define UARTLCR_LEN6    0x0001  /* data length : 6bit */
#define UARTLCR_LEN7    0x0002  /* data length : 7bit */
#define UARTLCR_LEN8    0x0003  /* data length : 8bit */
#define UARTLCR_STB1    0x0000  /* stop bit : 1 */
#define UARTLCR_STB2    0x0004  /* stop bit : 2(data length 6-8) */
#define UARTLCR_STB1_5  0x0004  /* stop bit : 1.5(data length 5) */
#define UARTLCR_PEN     0x0008  /* parity enabled */
#define UARTLCR_PDIS    0x0000  /* parity disabled */
#define UARTLCR_EVN     0x0010  /* even parity */
#define UARTLCR_ODD     0x0000  /* odd parity */
#define UARTLCR_SP      0x0020  /* stick parity */
#define UARTLCR_BRK     0x0040  /* break delivery */
#define UARTLCR_DLAB    0x0080  /* devisor latch access bit */

/* bit field of UARTLSR register */
#define UARTLSR_DR      0x0001  /* data ready */
#define UARTLSR_OE      0x0002  /* overrun error */
#define UARTLSR_PE      0x0004  /* parity error */
#define UARTLSR_FE      0x0008  /* framing error */
#define UARTLSR_BI      0x0010  /* break interrupt */
#define UARTLSR_THRE    0x0020  /* transmitter holding register empty */
#define UARTLSR_TEMT    0x0040  /* transmitter empty */
#define UARTLSR_ERF     0x0080  /* receiver FIFO error */

/* bit field of UARTFCR register */
#define UARTFCR_FE      0x0001  /* FIFO enable */
#define UARTFCR_FD      0x0000  /* FIFO disable */
#define UARTFCR_RFCLR   0x0002  /* receiver FIFO clear */
#define UARTFCR_TFCLR   0x0004  /* transmitter FIFO clear */
#define UARTFCR_OVR		0x0010	/* over run error mask */
#define UARTFCR_RFLV1   0x0000  /* RCVR FIFO interrupt trigger level : 1byte */
#define UARTFCR_RFLV4   0x0040  /* RCVR FIFO interrupt trigger level : 4byte */
#define UARTFCR_RFLV8   0x0080  /* RCVR FIFO interrupt trigger level : 8byte */
#define UARTFCR_RFLV14  0x00C0  /* RCVR FIFO interrupt trigger level : 14byte */

/* bit field of UARTMCR register */
#define UARTMCR_DTR     0x0001  /* data terminal ready */
#define UARTMCR_RTS     0x0002  /* request to send */
#define UARTMCR_LOOP    0x0010  /* loopback */

/* bit field of UARTMSR register */
#define UARTMSR_DCTS    0x0001  /* delta clear to send */
#define UARTMSR_DDSR    0x0002  /* delta data set ready */
#define UARTMSR_TERI    0x0004  /* trailing edge of ring endicator */
#define UARTMSR_DDCD    0x0008  /* delta data carrer detect */
#define UARTMSR_CTS     0x0010  /* clear to send */
#define UARTMSR_DSR     0x0020  /* data set ready */
#define UARTMSR_RI      0x0040  /* ring indicator */
#define UARTMSR_RLSD     0x0080  /* data carrer detect */

/* bit field of UARTIIR register */
#define UARTIIR_TP      0x0001  /* interrupt generated */
#define UARTIIR_MODEMI  0x0000  /* modem status interrupt */
#define UARTIIR_TRA     0x0002  /* transmitter interrupt */
#define UARTIIR_RCV     0x0004  /* receiver interrupt */
#define UARTIIR_LINE	0x0006	/* receive line error interrupt */
#define UARTIIR_TO      0x000C  /* time out interrupt */
#define UARTIIR_FM      0x00C0  /* FIFO mode */

/* bit field of UARTIER register */
#define UARTIER_ERBF    0x0001  /* enable received data available interrupt */
#define UARTIER_ETBEF   0x0002  /* enable transmitter holding register empty interrupt */
#define UARTIER_ELSI    0x0004  /* enable receiver line status interrupt */
#define UARTIER_EDSSI   0x0008  /* enable modem status interrupt */

/*****************************************************/
/*    port control register                           */
/*****************************************************/
#define PCR_BASE0	0xB7A00000  	/* base address */
#define PO0			(PCR_BASE0+0x00) 	/* port0(PA) output register */
#define PI0			(PCR_BASE0+0x04) 	/* port0(PA) input register */
#define PM0			(PCR_BASE0+0x08) 	/* port0(PA) Mode register */
#define IE0			(PCR_BASE0+0x0C) 	/* port0(PA) interrupt enable */
#define IM0			(PCR_BASE0+0x10) 	/* port0(PA) interrupt Mode register */
#define IS0			(PCR_BASE0+0x18) 	/* port0(PA) interrupt Status register*/

#define PCR_BASE1	0xB7A01000  	/* base address */
#define PO1			(PCR_BASE1+0x00) 	/* port1(PB) output register */
#define PI1			(PCR_BASE1+0x04) 	/* port1(PB) input register */
#define PM1			(PCR_BASE1+0x08) 	/* port1(PB) Mode register */
#define IE1			(PCR_BASE1+0x0C) 	/* port1(PB) interrupt enable */
#define IM1			(PCR_BASE1+0x10) 	/* port1(PB) interrupt Mode register */
#define IS1			(PCR_BASE1+0x18) 	/* port1(PB) interrupt Status register*/

#define PCR_BASE2	0xB7A02000  	/* base address */
#define PO2			(PCR_BASE2+0x00) 	/* port2(PC) output register */
#define PI2			(PCR_BASE2+0x04) 	/* port2(PC) input register */
#define PM2			(PCR_BASE2+0x08) 	/* port2(PC) Mode register */
#define IE2			(PCR_BASE2+0x0C) 	/* port2(PC) interrupt enable */
#define IM2			(PCR_BASE2+0x10) 	/* port2(PC) interrupt Mode register */
#define IS2			(PCR_BASE2+0x18) 	/* port2(PC) interrupt Status register*/

#define PCR_BASE3	0xB7A03000  	/* base address */
#define PO3			(PCR_BASE3+0x00) 	/* port3(PD) output register */
#define PI3			(PCR_BASE3+0x04) 	/* port3(PD) input register */
#define PM3			(PCR_BASE3+0x08) 	/* port3(PD) Mode register */
#define IE3			(PCR_BASE3+0x0C) 	/* port3(PD) interrupt enable */
#define IM3			(PCR_BASE3+0x10) 	/* port3(PD) interrupt Mode register */
#define IS3			(PCR_BASE3+0x18) 	/* port3(PD) interrupt Status register*/

#define PCR_BASE4	0xB7A04000  	/* base address */
#define PO4			(PCR_BASE4+0x00) 	/* port4(PE) output register */
#define PI4			(PCR_BASE4+0x04) 	/* port4(PE) input register */
#define PM4			(PCR_BASE4+0x08) 	/* port4(PE) Mode register */
#define IE4			(PCR_BASE4+0x0C) 	/* port4(PE) interrupt enable */
#define IM4			(PCR_BASE4+0x10) 	/* port4(PE) interrupt Mode register */
#define IS4			(PCR_BASE4+0x18) 	/* port4(PE) interrupt Status register*/

#define PCR_BASE5	0xB7A05000  	/* base address */
#define PO5			(PCR_BASE5+0x00) 	/* port5(PF) output register */
#define PI5			(PCR_BASE5+0x04) 	/* port5(PF) input register */
#define PM5			(PCR_BASE5+0x08) 	/* port5(PF) Mode register */
#define IE5			(PCR_BASE5+0x0C) 	/* port5(PF) interrupt enable */
#define IM5			(PCR_BASE5+0x10) 	/* port5(PF) interrupt Mode register */
#define IS5			(PCR_BASE5+0x18) 	/* port5(PF) interrupt Status register*/

#define PCR_BASE6	0xB7A06000  	/* base address */
#define PO6			(PCR_BASE6+0x00) 	/* port6(PG) output register */
#define PI6			(PCR_BASE6+0x04) 	/* port6(PG) input register */
#define PM6			(PCR_BASE6+0x08) 	/* port6(PG) Mode register */
#define IE6			(PCR_BASE6+0x0C) 	/* port6(PG) interrupt enable */
#define IM6			(PCR_BASE6+0x10) 	/* port6(PG) interrupt Mode register */
#define IS6			(PCR_BASE6+0x18) 	/* port6(PG) interrupt Status register*/

#define PCR_BASE7	0xB7A07000  	/* base address */
#define PO7			(PCR_BASE7+0x00) 	/* port7(PH) output register */
#define PI7			(PCR_BASE7+0x04) 	/* port7(PH) input register */
#define PM7			(PCR_BASE7+0x08) 	/* port7(PH) Mode register */
#define IE7			(PCR_BASE7+0x0C) 	/* port7(PH) interrupt enable */
#define IM7			(PCR_BASE7+0x10) 	/* port7(PH) interrupt Mode register */
#define IS7			(PCR_BASE7+0x18) 	/* port7(PH) interrupt Status register*/