nml67405x.h

uCos_II到ARM7的移植

/**********************************************************************************/
/*                                                                                */
/*    Copyright (C) 2005 Oki Electric Industry Co., LTD.                          */
/*                                                                                */
/*    System Name    :  ML67Q4051/ML67Q4061	                                      */
/*    Module Name    :  ML67Q4061 header file				                      */
/*    File   Name    :  ML674061.h                                                */
/*    Revision       :  1.00		                                              */
/*    Date           :  2005/11/05                                                */
/*                                                                                */
/**********************************************************************************/
#ifndef ML674061_H
#define ML674061_H

#ifdef __cplusplus
extern "C" {
#endif


/*****************************************************/
/*    common type definition                         */
/*****************************************************/
typedef char    BYTE;   /* byte */
typedef short   HWORD;  /* half word */
typedef long    WORD;   /* word */
typedef unsigned char   UBYTE;  /* unsigned byte */
typedef unsigned short  UHWORD; /* unsigned half word */
typedef unsigned long   UWORD;  /* unsigned word */


/*****************************************************/
/*    internal I/O input/output macro                */
/*****************************************************/
#define get_value(n)    (*((volatile UBYTE *)(n)))          /* byte input */
#define put_value(n,c)  (*((volatile UBYTE *)(n)) = (c))    /* byte output */
#define get_hvalue(n)   (*((volatile UHWORD *)(n)))         /* half word input */
#define put_hvalue(n,c) (*((volatile UHWORD *)(n)) = (c))   /* half word output */
#define get_wvalue(n)   (*((volatile UWORD *)(n)))          /* word input */
#define put_wvalue(n,c) (*((volatile UWORD *)(n)) = (c))    /* word output */
#define set_bit(n,c)    (*((volatile UBYTE *)(n))|= (c))    /* byte bit set */
#define clr_bit(n,c)    (*((volatile UBYTE *)(n))&=~(c))    /* byte bit clear */
#define set_hbit(n,c)   (*((volatile UHWORD *)(n))|= (c))   /* half word bit set */
#define clr_hbit(n,c)   (*((volatile UHWORD *)(n))&=~(c))   /* half word bit clear */
#define set_wbit(n,c)   (*((volatile UWORD *)(n))|= (c))    /* word bit set */
#define clr_wbit(n,c)   (*((volatile UWORD *)(n))&=~(c))    /* word bit clear */

/*------------------------------ uPLAT-7B core -----------------------------------*/
/*****************************************************/
/*    interrupt control register                     */
/*****************************************************/
#define ICR_BASE    0x78000000      /* base address of interrupt control register */
#define IRQ         (ICR_BASE+0x00) /* IRQ register */
#define IRQS        (ICR_BASE+0x04) /* IRQ soft register */
#define FIQ         (ICR_BASE+0x08) /* FIQ register */
#define FIQRAW      (ICR_BASE+0x0C) /* FIQRAW status register */
#define FIQEN       (ICR_BASE+0x10) /* FIQ enable register */
#define IRN         (ICR_BASE+0x14) /* IRQ number register */
#define CIL         (ICR_BASE+0x18) /* current IRQ level register */
#define IRL         (ICR_BASE+0x1C) /* IRQ level register */
#define ILC0        (ICR_BASE+0x20) /* IRQ level control register 0 */
#define ILC1        (ICR_BASE+0x24) /* IRQ level control register 1 */
#define CILCL       (ICR_BASE+0x28) /* current IRQ level clear register */
#define CILE        (ICR_BASE+0x2C) /* current IRQ level encode register */

/* bit field of IRQ register */
#define IRQ_nIR0    0x00000001  /* nIR[0] */
#define IRQ_nIR1    0x00000002  /* nIR[1] */
#define IRQ_nIR2    0x00000004  /* nIR[2] */
#define IRQ_nIR3    0x00000008  /* nIR[3] */
#define IRQ_nIR4    0x00000010  /* nIR[4] */
#define IRQ_nIR5    0x00000020  /* nIR[5] */
#define IRQ_nIR6    0x00000040  /* nIR[6] */
#define IRQ_nIR7    0x00000080  /* nIR[7] */
#define IRQ_nIR8    0x00000100  /* nIR[8] */
#define IRQ_nIR9    0x00000200  /* nIR[9] */
#define IRQ_nIR10   0x00000400  /* nIR[10] */
#define IRQ_nIR11   0x00000800  /* nIR[11] */
#define IRQ_nIR12   0x00001000  /* nIR[12] */
#define IRQ_nIR13   0x00002000  /* nIR[13] */
#define IRQ_nIR14   0x00004000  /* nIR[14] */
#define IRQ_nIR15   0x00008000  /* nIR[15] */

/* bit field of CIL register */
#define CIL_INT_LV1 0x00000002  /* interrupt level 1 */
#define CIL_INT_LV2 0x00000004  /* interrupt level 2 */
#define CIL_INT_LV3 0x00000008  /* interrupt level 3 */
#define CIL_INT_LV4 0x00000010  /* interrupt level 4 */
#define CIL_INT_LV5 0x00000020  /* interrupt level 5 */
#define CIL_INT_LV6 0x00000040  /* interrupt level 6 */
#define CIL_INT_LV7 0x00000080  /* interrupt level 7 */

/* bit field of ILC0 register */
#define ILC0_INT_LV1    0x11111111  /* interrupt level 1 */
#define ILC0_INT_LV2    0x22222222  /* interrupt level 2 */
#define ILC0_INT_LV3    0x33333333  /* interrupt level 3 */
#define ILC0_INT_LV4    0x44444444  /* interrupt level 4 */
#define ILC0_INT_LV5    0x55555555  /* interrupt level 5 */
#define ILC0_INT_LV6    0x66666666  /* interrupt level 6 */
#define ILC0_INT_LV7    0x77777777  /* interrupt level 7 */
#define ILC0_ILR0       0x00000007  /* nIR[0] */
#define ILC0_ILR1       0x00000070  /* nIR[1],nIR[2],nIR[3] */
#define ILC0_ILR4       0x00070000  /* nIR[4],nIR[5] */
#define ILC0_ILR6       0x07000000  /* nIR[6],nIR[7] */

/* bit field of ILC1 register */
#define ILC1_INT_LV1    0x11111111  /* interrupt level 1 */
#define ILC1_INT_LV2    0x22222222  /* interrupt level 2 */
#define ILC1_INT_LV3    0x33333333  /* interrupt level 3 */
#define ILC1_INT_LV4    0x44444444  /* interrupt level 4 */
#define ILC1_INT_LV5    0x55555555  /* interrupt level 5 */
#define ILC1_INT_LV6    0x66666666  /* interrupt level 6 */
#define ILC1_INT_LV7    0x77777777  /* interrupt level 7 */
#define ILC1_ILR8       0x00000007  /* nIR[8] */
#define ILC1_ILR9       0x00000070  /* nIR[9] */
#define ILC1_ILR10      0x00000700  /* nIR[10] */
#define ILC1_ILR11      0x00007000  /* nIR[11] */
#define ILC1_ILR12      0x00070000  /* nIR[12] */
#define ILC1_ILR13      0x00700000  /* nIR[13] */
#define ILC1_ILR14      0x07000000  /* nIR[14] */
#define ILC1_ILR15      0x70000000  /* nIR[15] */

/* bit field of CILCL register */
#define CILCL_CLEAR     0x01        /* most significant '1' bit of CIL is cleared */

/*****************************************************/
/*    external memory control register               */
/*****************************************************/
#define EMCR_BASE   0x78100000          /* base address */
#define BWC         (EMCR_BASE+0x00)    /* bus width control register */
#define ROMAC       (EMCR_BASE+0x04)    /* external ROM access control register */
#define RAMAC       (EMCR_BASE+0x08)    /* external SRAM access control register */
#define IO0AC       (EMCR_BASE+0x0C)    /* external IO0 access control register */
#define IO1AC       (EMCR_BASE+0x10)    /* external IO1 access control register */

/*****************************************************/
/*    system control register                        */
/*****************************************************/
#define SCR_BASE    0xB8000000      /* base address */
#define IDR         (SCR_BASE+0x00) /* ID register */
#define CLKSTP      (SCR_BASE+0x04) /* clock stop register */
#define RMPCON      (SCR_BASE+0x10) /* remap control register */

#define	SCR_BASE2	0xB7000000		/* base address */
#define PECLKCNT	(SCR_BASE2+0x00)	/* peripheral clock control register */
#define PERSTCNT	(SCR_BASE2+0x04)	/* peripheral reset control register */
#define PLL1		(SCR_BASE2+0x08)	/* PLL1 control register */
#define PLL2		(SCR_BASE2+0x0C)	/* PLL2 control register */
#define CLKCNT		(SCR_BASE2+0x10)	/* clock control register */
#define CLKSTPCNT	(SCR_BASE2+0x14)	/* clock stop control register */
#define DMARQCNT	(SCR_BASE2+0x1C)	/* DMA request select register */
#define LSICNT		(SCR_BASE2+0x20)	/* LSI control register */
#define	PORTSEL1	(SCR_BASE2+0x24)	/* port control register 1 */
#define	PORTSEL2	(SCR_BASE2+0x28)	/* port control register 2 */
#define	PORTSEL3	(SCR_BASE2+0x2C)	/* port control register 3 */
#define	PORTSEL4	(SCR_BASE2+0x30)	/* port control register 4 */
#define	PORTSEL5	(SCR_BASE2+0x34)	/* port control register 5 */
#define FTMSEL		(SCR_BASE2+0x40)	/* FTM control register */
#define CKWT        (SCR_BASE2+0x44) 	/* clock wait register */
#define FLACON		(SCR_BASE2+0x100)	/* Flash memory control register */

/* bit field of CLKSTP register */
#define CLKSTP_CPUG  0x04        /* CPU group HALT */
#define CLKSTP_TIC   0x02        /* TIC HALT */
#define CLKSTP_SIO0  0x01        /* SIO HALT */
#define CLKSTP_STOP  0x80        /* clock stop */

/* bit field of CLKSTP register */
#define CLKCNT_PLLSEL		0x00000003
#define CLKCNT_CLKDIVA		0x0000001C
#define CLKCNT_CLKDIVB		0x00000060
#define CLKCNT_SRCSEL		0x00000300
#define CLKCNT_APBDIV		0x00000C00
#define CLKCNT_AUDIOSEL		0x00003000
#define CLKCNT_PLLENA		0x00010000
#define CLKCNT_PLLENB		0x00020000
#define CLKCNT_RINGOSCEN	0x00040000
#define CLKCNT_SYSCLKEN		0x00080000
#define CLKCNT_RTCCLKEN		0x00100000

/* bit field of CLKSTP register */
#define LSICNT_I2SOUT	0x00000001
#define LSICNT_I2CNFON	0x00000010
#define LSICNT_JTAGE	0x00000100

/* bit field of PORTSEL1 register */
#define PORTSEL1_PA6	0x00003000
#define PORTSEL1_PB0	0x00030000
#define PORTSEL1_PB1	0x000C0000
#define PORTSEL1_PB2	0x00300000
#define PORTSEL1_PB3	0x00C00000
#define PORTSEL1_PB4	0x03000000
#define PORTSEL1_PB5	0x0C000000

/*****************************************************/
/*    system timer control register                  */
/*****************************************************/
#define STCR_BASE   0xB8001000          /* base address */
#define TMEN        (STCR_BASE+0x04)    /* timer enable register */
#define TMRLR       (STCR_BASE+0x08)    /* timer reload register */
#define TMOVF       (STCR_BASE+0x10)    /* overflow register */

/* bit field of TMEN register */
#define TMEN_TCEN   0x01        /* timer enabled */

/* bit field of TMOVF register */
#define TMOVF_OVF   0x01        /* overflow generated */


/*****************************************************/
/*    SIO control register                           */
/*****************************************************/
#define SC_BASE     0xB8002000      /* base address */
#define SIOBUF      (SC_BASE+0x00)  /* transmiting/receiving buffer register */
#define SIOSTA      (SC_BASE+0x04)  /* SIO status register */
#define SIOCON      (SC_BASE+0x08)  /* SIO control register */
#define SIOBCN      (SC_BASE+0x0C)  /* baud rate control register */
#define SIOBT       (SC_BASE+0x14)  /* baud rate timer register */
#define SIOTCN      (SC_BASE+0x18)  /* SIO test control register */

/* bit field of SIOSTA register */
#define SIOSTA_FERR     0x0001      /* framing error */
#define SIOSTA_OERR     0x0002      /* overrun error */
#define SIOSTA_PERR     0x0004      /* parity error */
#define SIOSTA_RVIRQ    0x0010      /* receive ready */
#define SIOSTA_TRIRQ    0x0020      /* transmit ready */

/* bit field of SIOCON register */
#define SIOCON_LN7      0x0001      /* data length : 7bit */
#define SIOCON_LN8      0x0000      /* data length : 8bit */
#define SIOCON_PEN      0x0002      /* parity enabled */
#define SIOCON_PDIS     0x0000      /* parity disabled */
#define SIOCON_EVN      0x0004      /* even parity */
#define SIOCON_ODD      0x0000      /* odd parity */
#define SIOCON_TSTB1    0x0008      /* stop bit : 1 */
#define SIOCON_TSTB2    0x0000      /* stop bit : 2 */

/* bit field of SIOBCN register */
#define SIOBCN_BGRUN    0x0010      /* count start */

/* bit field of SIOTCN register */
#define SIOTCN_MFERR    0x0001      /* generate framin error */
#define SIOTCN_MPERR    0x0002      /* generate parity error */
#define SIOTCN_LBTST    0x0080      /* loop back test */


/*---------------------------------- ML674051/61 ------------------------------------*/
/*****************************************************/
/*    timer control register                         */
/*****************************************************/
#define FTM_BASE	0xB7F00000  /* base address */
#define FTM0CON		(FTM_BASE+0x00) /* timer0 control register */
#define FTM0ST		(FTM_BASE+0x04)	/* timer0 status register */
#define FTM0C		(FTM_BASE+0x08) /* timer0 counter register */
#define FTM0R		(FTM_BASE+0x0C)	/* timer0 register */
#define FTM0GR		(FTM_BASE+0x10)	/* timer0 wide use register */
#define FTM0IOLV	(FTM_BASE+0x14)	/* timer0 I/O level register */
#define FTM0OUT		(FTM_BASE+0x18)	/* timer0 out register */
#define FTM0IER		(FTM_BASE+0x1C) /* timer0 interrupt enable register */
#define FTM1CON		(FTM_BASE+0x20) /* timer1 control register */
#define FTM1ST		(FTM_BASE+0x24)	/* timer1 status register */
#define FTM1C		(FTM_BASE+0x28) /* timer1 counter register */
#define FTM1R		(FTM_BASE+0x2C)	/* timer1 register */
#define FTM1GR		(FTM_BASE+0x30)	/* timer1 wide use register */
#define FTM1IOLV	(FTM_BASE+0x34)	/* timer1 I/O level register */
#define FTM1OUT		(FTM_BASE+0x38)	/* timer1 out register */
#define FTM1IER		(FTM_BASE+0x3C) /* timer1 interrupt enable register */
#define FTM2CON		(FTM_BASE+0x40) /* timer2 control register */
#define FTM2ST		(FTM_BASE+0x44)	/* timer2 status register */
#define FTM2C		(FTM_BASE+0x48) /* timer2 counter register */
#define FTM2R		(FTM_BASE+0x4C)	/* timer2 register */
#define FTM2GR		(FTM_BASE+0x50)	/* timer2 wide use register */