plf_io.h

ecos在三星44b0上的移植

#define study_UART_BRDIV		0x0028

#define study_UART_LCON_5_DBITS		0x00
#define study_UART_LCON_6_DBITS		0x01
#define study_UART_LCON_7_DBITS		0x02
#define study_UART_LCON_8_DBITS		0x03
#define study_UART_LCON_1_SBITS		0x00
#define study_UART_LCON_2_SBITS		0x04
#define study_UART_LCON_NO_PARITY	0x00
#define study_UART_LCON_ODD_PARITY	0x20
#define study_UART_LCON_EVEN_PARITY	0x28
#define study_UART_LCON_1_PARITY	0x30
#define study_UART_LCON_0_PARITY	0x38
#define study_UART_LCON_IR		0x40

#define study_UART_CON_RXM_MASK		0x03
#define study_UART_CON_RXM_INT		0x01
#define study_UART_CON_RXM_BDMA0	0x02
#define study_UART_CON_RXM_BDMA1	0x03

#define study_UART_CON_TXM_MASK		0x0c
#define study_UART_CON_TXM_INT		0x04
#define study_UART_CON_TXM_BDMA0	0x08
#define study_UART_CON_TXM_BDMA1	0x0c

#define study_UART_STAT_RXOK		0x01	// rx ready
#define study_UART_STAT_TXE		0x02    // tx empty
#define study_UART_STAT_TC		0x04    // tx complete


//-----------------------------------------------------------------------------
// SIO

#define study_SIOCON			(study_REG_BASE + 0x114000)
#define study_SIODAT			(study_REG_BASE + 0x114004)
#define study_SBRDR			(study_REG_BASE + 0x114008)
#define study_ITVCNT			(study_REG_BASE + 0x11400C)
#define study_DCNTZ			(study_REG_BASE + 0x114010)

//-----------------------------------------------------------------------------
// IIS

#define study_IISCON			(study_REG_BASE + 0x118000)
#define study_IISMOD			(study_REG_BASE + 0x118004)
#define study_IISPSR			(study_REG_BASE + 0x118008)
#define study_IISFIFCON			(study_REG_BASE + 0x11800C)
#define study_IISFIF			(study_REG_BASE + 0x118010)


//-----------------------------------------------------------------------------
// PIO

#define study_PCONA			(study_REG_BASE + 0x120000)
#define study_PDATA			(study_REG_BASE + 0x120004)
#define study_PCONB			(study_REG_BASE + 0x120008)
#define study_PDATB			(study_REG_BASE + 0x12000C)
#define study_PCONC			(study_REG_BASE + 0x120010)
#define study_PDATC			(study_REG_BASE + 0x120014)
#define study_PUPC			(study_REG_BASE + 0x120018)
#define study_PCOND			(study_REG_BASE + 0x12001C)
#define study_PDATD			(study_REG_BASE + 0x120020)
#define study_PUPD			(study_REG_BASE + 0x120024)
#define study_PCONE			(study_REG_BASE + 0x120028)
#define study_PDATE			(study_REG_BASE + 0x12002C)
#define study_PUPE			(study_REG_BASE + 0x120030)
#define study_PCONF			(study_REG_BASE + 0x120034)
#define study_PDATF			(study_REG_BASE + 0x120038)
#define study_PUPF			(study_REG_BASE + 0x12003C)
#define study_PCONG			(study_REG_BASE + 0x120040)
#define study_PDATG			(study_REG_BASE + 0x120044)
#define study_PUPG			(study_REG_BASE + 0x120048)
#define study_SPUCR			(study_REG_BASE + 0x12004C)
#define study_EXTINT			(study_REG_BASE + 0x120050)
#define study_EXTINPND			(study_REG_BASE + 0x120054)

//-----------------------------------------------------------------------------
// WATCH DOG 

#define study_WTCON			(study_REG_BASE + 0x130000)
#define study_WTDAT			(study_REG_BASE + 0x130004)
#define study_WTCNT			(study_REG_BASE + 0x130008)

//-----------------------------------------------------------------------------
// A/D

#define study_ADCCON			(study_REG_BASE + 0x140000)
#define study_ADCPSR			(study_REG_BASE + 0x140004)
#define study_ADCDAT			(study_REG_BASE + 0x140008)

//-----------------------------------------------------------------------------
// PWM Timers

#define study_TCFG0			(study_REG_BASE + 0x150000)
#define study_TCFG1			(study_REG_BASE + 0x150004)
#define study_TCON			(study_REG_BASE + 0x150008)
#define study_TCNTB0			(study_REG_BASE + 0x15000C)
#define study_TCMPB0			(study_REG_BASE + 0x150010)
#define study_TCNTO0			(study_REG_BASE + 0x150014)
#define study_TCNTB1			(study_REG_BASE + 0x150018)
#define study_TCMPB1			(study_REG_BASE + 0x15001C)
#define study_TCNTO1			(study_REG_BASE + 0x150020)
#define study_TCNTB2			(study_REG_BASE + 0x150024)
#define study_TCMPB2			(study_REG_BASE + 0x150028)
#define study_TCNTO2			(study_REG_BASE + 0x15002C)
#define study_TCNTB3			(study_REG_BASE + 0x150030)
#define study_TCMPB3			(study_REG_BASE + 0x150034)
#define study_TCNTO3			(study_REG_BASE + 0x150038)
#define study_TCNTB4			(study_REG_BASE + 0x15003C)
#define study_TCMPB4			(study_REG_BASE + 0x150040)
#define study_TCNTO4			(study_REG_BASE + 0x150044)
#define study_TCNTB5			(study_REG_BASE + 0x150048)
#define study_TCNTO5			(study_REG_BASE + 0x15004C)
                                                                 

#define study_TCON_T0_RUN		0x00000001
#define study_TCON_T0_UPDATE		0x00000002
#define study_TCON_T0_INV		0x00000004
#define study_TCON_T0_RELOAD		0x00000008

#define study_TCON_DEAD			0x00000010

#define study_TCON_T1_RUN		0x00000100
#define study_TCON_T1_UPDATE		0x00000200
#define study_TCON_T1_INV		0x00000400
#define study_TCON_T1_RELOAD		0x00000800

#define study_TCON_T2_RUN		0x00001000
#define study_TCON_T2_UPDATE		0x00002000
#define study_TCON_T2_INV		0x00004000
#define study_TCON_T2_RELOAD		0x00008000

#define study_TCON_T3_RUN		0x00010000
#define study_TCON_T3_UPDATE		0x00020000
#define study_TCON_T3_INV		0x00040000
#define study_TCON_T3_RELOAD		0x00080000

#define study_TCON_T4_RUN		0x00100000
#define study_TCON_T4_UPDATE		0x00200000
#define study_TCON_T4_INV		0x00400000
#define study_TCON_T4_RELOAD		0x00800000

#define study_TCON_T5_RUN		0x01000000
#define study_TCON_T5_UPDATE		0x02000000
#define study_TCON_T5_RELOAD		0x04000000


//-----------------------------------------------------------------------------
// IIC

//-----------------------------------------------------------------------------
// RTC

//-----------------------------------------------------------------------------
// POWER & CLOCK

#define study_PLLCON			(study_REG_BASE + 0x180000)
#define study_CLKCON			(study_REG_BASE + 0x180004)
#define study_CLKSLOW			(study_REG_BASE + 0x180008)
#define study_LOCKTIME			(study_REG_BASE + 0x18000C)

//-----------------------------------------------------------------------------
// INTC

#define study_INTCON			(study_REG_BASE + 0x200000)
#define study_INTPND			(study_REG_BASE + 0x200004)
#define study_INTMOD			(study_REG_BASE + 0x200008)
#define study_INTMSK			(study_REG_BASE + 0x20000C)
#define study_IPSLV			(study_REG_BASE + 0x200010)
#define study_IPMST			(study_REG_BASE + 0x200014)
#define study_ICSLV			(study_REG_BASE + 0x200018)
#define study_ICMST			(study_REG_BASE + 0x20001C)
#define study_IISPR			(study_REG_BASE + 0x200020)
#define study_IISPC			(study_REG_BASE + 0x200024)
#define study_FISPR			(study_REG_BASE + 0x200038)
#define study_FISPC			(study_REG_BASE + 0x20003C)

#define study_INTMSK_GLOBAL         (1<<26)

//-----------------------------------------------------------------------------
// LCD

//-----------------------------------------------------------------------------
// Cache
#define study_CACHE_SET0_ADDR       0x10000000
#define study_CACHE_SET1_ADDR       0x10000800
#define study_CACHE_SET2_ADDR       0x10001000
#define study_CACHE_SET3_ADDR       0x10001800
#define study_CACHE_TAG_ADDR        0x10002000

//-----------------------------------------------------------------------------
// Memory map is 1-1

#define CYGARC_PHYSICAL_ADDRESS(_x_) (_x_)

//-----------------------------------------------------------------------------
//

//Bank 0 parameter
#define B0_Tacs			0x0	//0clk
#define B0_Tcos			0x0	//0clk
#define B0_Tacc			0x6	//10clk
#define B0_Tcoh			0x0	//0clk
#define B0_Tah			0x0	//0clk
#define B0_Tacp			0x0	//0clk
#define B0_PMC			0x0	//normal(1data)

//Bank 1 parameter
#define B1_Tacs			0x3	//4clk
#define B1_Tcos			0x3	//4clk
#define B1_Tacc			0x7	//14clk
#define B1_Tcoh			0x3	//4clk
#define B1_Tah			0x3	//4clk
#define B1_Tacp			0x3	//6clk
#define B1_PMC			0x0	//normal(1data)

//Bank 2 parameter
#define B2_Tacs			0x3	//4clk
#define B2_Tcos			0x3	//4clk
#define B2_Tacc			0x7	//14clk
#define B2_Tcoh			0x3	//4clk
#define B2_Tah			0x3	//4clk
#define B2_Tacp			0x3	//6clk
#define B2_PMC			0x0	//normal(1data)

//Bank 3 parameter
#define B3_Tacs			0x3	//4clk
#define B3_Tcos			0x3	//4clk
#define B3_Tacc			0x7	//14clk
#define B3_Tcoh			0x3	//4clk
#define B3_Tah			0x3	//4clk
#define B3_Tacp			0x3	//6clk
#define B3_PMC			0x0	//normal(1data)

//Bank 4 parameter
#define B4_Tacs			0x3	//4clk
#define B4_Tcos			0x3	//4clk
#define B4_Tacc			0x7	//14clk
#define B4_Tcoh			0x3	//4clk
#define B4_Tah			0x3	//4clk
#define B4_Tacp			0x3	//6clk
#define B4_PMC			0x0	//normal(1data)

//Bank 5 parameter
#define B5_Tacs			0x3	//4clk
#define B5_Tcos			0x3	//4clk
#define B5_Tacc			0x7	//14clk
#define B5_Tcoh			0x3	//4clk
#define B5_Tah			0x3	//4clk
#define B5_Tacp			0x3	//6clk
#define B5_PMC			0x0	//normal(1data)

//Bank 6(if SROM) parameter
#define B6_Tacs			0x3	//4clk
#define B6_Tcos			0x3	//4clk
#define B6_Tacc			0x7	//14clk
#define B6_Tcoh			0x3	//4clk
#define B6_Tah			0x3	//4clk
#define B6_Tacp			0x3	//6clk
#define B6_PMC			0x0	//normal(1data)

//Bank 7(if SROM) parameter
#define B7_Tacs			0x3	//4clk
#define B7_Tcos			0x3	//4clk
#define B7_Tacc			0x7	//14clk
#define B7_Tcoh			0x3	//4clk
#define B7_Tah			0x3	//4clk
#define B7_Tacp			0x3	//6clk
#define B7_PMC			0x0	//normal(1data)

//Bank 6 parameter
//"SDRAM"		//MT=11(SDRAM)
#define B6_MT			0x3	//SDRAM
#define B6_Trcd			0x0	//2clk
#define B6_SCAN			0x0	//8bit


//Bank 7 parameter
//"SDRAM"		//MT=11(SDRAM)
#define B7_MT			0x3	//SDRAM
#define B7_Trcd			0x0	//2clk
#define B7_SCAN			0x0	//8bit


//REFRESH parameter
#define REFEN			0x1	//Refresh enable
#define TREFMD			0x0	//CBR(CAS before RAS)/Auto refresh
#define Trp				0x0	//2clk
#define Trc				0x1	//5clk
#define Tchr			0x2	//3clk
#define REFCNT			1113	//period=15.6us, MCLK=60Mhz

//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_HAL_PLF_IO_H