📄 plf_io.h
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#ifndef CYGONCE_HAL_PLF_IO_H
#define CYGONCE_HAL_PLF_IO_H
//=============================================================================
//
// plf_io.h
//
// Platform specific registers
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2001-03-16
// Purpose: ARM/study platform specific registers
// Description:
// Usage: #include <cyg/hal/plf_io.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
#define study_REG_BASE 0x01c00000
// -----------------------------------------------------------------------------
// System config (register bases and caching)
#define study_SYSCFG (study_REG_BASE + 0x0000)
#define study_SYSCFG_CM_MASK 0x00000006
#define study_SYSCFG_CM_0R_0C 0x00000000
#define study_SYSCFG_CM_4R_4C 0x00000002
#define study_SYSCFG_CM_0R_8C 0x00000006
#define study_SYSCFG_WE 0x00000008
#define study_SYSCFG_SE 0x00000001
#define study_NCACHBE0 (study_REG_BASE + 0x0004)
#define study_NCACHBE0_SA0_MASK 0x0000ffff
#define study_NCACHBE0_SE0_MASK 0xffff0000
#define study_NCACHBE1 (study_REG_BASE + 0x0008)
#define study_NCACHBE1_SA1_MASK 0x0000ffff
#define study_NCACHBE1_SE1_MASK 0xffff0000
#define study_SBUSCON (study_REG_BASE + 0x40000)
#define study_SBUSCON_FIX 0x80000000
#define study_SBUSCON_MASK 3
#define study_SBUSCON_PRI_0 0
#define study_SBUSCON_PRI_1 1
#define study_SBUSCON_PRI_2 2
#define study_SBUSCON_PRI_3 3
#define study_SBUSCON_S_LCD_DMA_shift 14
#define study_SBUSCON_S_ZDMA_shift 12
#define study_SBUSCON_S_BDMA_shift 10
#define study_SBUSCON_S_nBREQ_shift 8
#define study_SBUSCON_LCD_DMA_shift 6
#define study_SBUSCON_ZDMA_shift 4
#define study_SBUSCON_BDMA_shift 2
#define study_SBUSCON_nBREQ_shift 0
//-----------------------------------------------------------------------------
// Memory banks data width
#define study_BWSCON (study_REG_BASE + 0x80000)
#define study_BWSCON_DW_MASK 3
#define study_BWSCON_DW_8BIT 0
#define study_BWSCON_DW_16BIT 1
#define study_BWSCON_DW_32BIT 2
#define study_BWSCON_DW0_shift 1
#define study_BWSCON_DW1_shift 4
#define study_BWSCON_DW2_shift 8
#define study_BWSCON_DW3_shift 12
#define study_BWSCON_DW4_shift 16
#define study_BWSCON_DW5_shift 20
#define study_BWSCON_DW6_shift 24
#define study_BWSCON_DW7_shift 28
#define study_BWSCON_WS1_shift 6
#define study_BWSCON_WS2_shift 10
#define study_BWSCON_WS3_shift 14
#define study_BWSCON_WS4_shift 18
#define study_BWSCON_WS5_shift 22
#define study_BWSCON_WS6_shift 26
#define study_BWSCON_WS7_shift 30
#define study_BWSCON_ST1_shift 7
#define study_BWSCON_ST2_shift 11
#define study_BWSCON_ST3_shift 15
#define study_BWSCON_ST4_shift 19
#define study_BWSCON_ST5_shift 23
#define study_BWSCON_ST6_shift 27
#define study_BWSCON_ST7_shift 31
#define study_BWSCON_ENDIAN_L 0
#define study_BWSCON_ENDIAN_B 1
// -----------------------------------------------------------------------------
// Bank locations and timing
#define study_BANKCON0 (study_REG_BASE + 0x80004)
#define study_BANKCON1 (study_REG_BASE + 0x80008)
#define study_BANKCON2 (study_REG_BASE + 0x8000c)
#define study_BANKCON3 (study_REG_BASE + 0x80010)
#define study_BANKCON4 (study_REG_BASE + 0x80014)
#define study_BANKCON5 (study_REG_BASE + 0x80018)
#define study_BANKCON6 (study_REG_BASE + 0x8001c)
#define study_BANKCON7 (study_REG_BASE + 0x80020)
#define study_ROMCON_PMC_MASK 0x00000003
#define study_ROMCON_PMC_1 0x00000000
#define study_ROMCON_PMC_4 0x00000001
#define study_ROMCON_PMC_8 0x00000002
#define study_ROMCON_PMC_16 0x00000003
#define study_ROMCON_TPAC_MASK 0x0000000c
#define study_ROMCON_TPAC_2 0x00000000
#define study_ROMCON_TPAC_3 0x00000004
#define study_ROMCON_TPAC_4 0x00000008
#define study_ROMCON_TPAC_6 0x0000000c
#define study_ROMCON_TCAH_MASK 0x00000030
#define study_ROMCON_TCAH_0 0x00000000
#define study_ROMCON_TCAH_1 0x00000010
#define study_ROMCON_TCAH_2 0x00000020
#define study_ROMCON_TCAH_4 0x00000030
#define study_ROMCON_TOCH_MASK 0x000000c0
#define study_ROMCON_TOCH_0 0x00000000
#define study_ROMCON_TOCH_1 0x00000040
#define study_ROMCON_TOCH_2 0x00000080
#define study_ROMCON_TOCH_4 0x000000c0
#define study_ROMCON_TACC_MASK 0x00000700
#define study_ROMCON_TACC_1 0x00000000
#define study_ROMCON_TACC_2 0x00000100
#define study_ROMCON_TACC_3 0x00000200
#define study_ROMCON_TACC_4 0x00000300
#define study_ROMCON_TACC_6 0x00000400
#define study_ROMCON_TACC_8 0x00000500
#define study_ROMCON_TACC_10 0x00000600
#define study_ROMCON_TACC_14 0x00000700
#define study_ROMCON_TCOS_MASK 0x00001800
#define study_ROMCON_TCOS_0 0x00000000
#define study_ROMCON_TCOS_1 0x00000800
#define study_ROMCON_TCOS_2 0x00001000
#define study_ROMCON_TCOS_4 0x00001800
#define study_ROMCON_TACS_MASK 0x00006000
#define study_ROMCON_TACS_0 0x00000000
#define study_ROMCON_TACS_1 0x00002000
#define study_ROMCON_TACS_2 0x00004000
#define study_ROMCON_TACS_4 0x00006000
// only bank6/7
#define study_ROMCON_MT_MASK 0x00018000
#define study_ROMCON_MT_ROM_SRAM 0x00000000
#define study_ROMCON_MT_FP_DRAM 0x00008000
#define study_ROMCON_MT_EDO_DRAM 0x00010000
#define study_ROMCON_MT_SDRAM 0x00018000
// only FP_DRAM / EDO_DRAM
#define study_ROMCON_CAN_MASK 0x00000003
#define study_ROMCON_CAN_8 0x00000000
#define study_ROMCON_CAN_9 0x00000001
#define study_ROMCON_CAN_10 0x00000002
#define study_ROMCON_CAN_11 0x00000003
#define study_ROMCON_TCP 0x00000004
#define study_ROMCON_TCAS 0x00000008
#define study_ROMCON_TRCD_MASK 0x00000030
#define study_ROMCON_TRCD_1 0x00000000
#define study_ROMCON_TRCD_2 0x00000010
#define study_ROMCON_TRCD_3 0x00000020
#define study_ROMCON_TRCD_4 0x00000030
// only SDRAM
#define study_ROMCON_SCAN_MASK 0x00000003
#define study_ROMCON_SCAN_8 0x00000000
#define study_ROMCON_SCAN_9 0x00000001
#define study_ROMCON_SCAN_10 0x00000002
#define study_ROMCON_STRCD_MASK 0x0000000c
#define study_ROMCON_STRCD_2 0x00000000
#define study_ROMCON_STRCD_3 0x00000004
#define study_ROMCON_STRCD_4 0x00000008
#define study_REFRESH (study_REG_BASE + 0x80024)
#define study_REFRESH_CNT 0x000007ff
#define study_REFRESH_TCHR_MASK 0x00030000
#define study_REFRESH_TCHR_1 0x00000000
#define study_REFRESH_TCHR_2 0x00010000
#define study_REFRESH_TCHR_3 0x00020000
#define study_REFRESH_TCHR_4 0x00020000
#define study_REFRESH_TRC_MASK 0x000C0000
#define study_REFRESH_TRC_4 0x00000000
#define study_REFRESH_TRC_5 0x00040000
#define study_REFRESH_TRC_6 0x00080000
#define study_REFRESH_TRC_7 0x000C0000
#define study_REFRESH_TRP_MASK 0x00300000
// DRAM
#define study_REFRESH_TRP_15 0x00000000
#define study_REFRESH_TRP_25 0x00100000
#define study_REFRESH_TRP_35 0x00200000
#define study_REFRESH_TRP_45 0x00300000
// SDRAM
#define study_REFRESH_TRP_2 0x00000000
#define study_REFRESH_TRP_3 0x00100000
#define study_REFRESH_TRP_4 0x00200000
#define study_REFRESH_TREFMD 0x00400000
#define study_REFRESH_REFEN 0x00800000
#define study_BANKSIZE (study_REG_BASE + 0x80028)
#define study_BANKSIZE_BK67MAP_MASK 0x00000007
#define study_BANKSIZE_BK67MAP_32M_32M 0x00000000
#define study_BANKSIZE_BK67MAP_2M_2M 0x00000004
#define study_BANKSIZE_BK67MAP_4M_4M 0x00000005
#define study_BANKSIZE_BK67MAP_8M_8M 0x00000006
#define study_BANKSIZE_BK67MAP_16M_16M 0x00000007
#define study_BANKSIZE_SCLKEN 0x00000010
#define study_MRSRB6 (study_REG_BASE + 0x8002C)
#define study_MRSRB7 (study_REG_BASE + 0x80030)
#define study_MRSRB_CL_MASK 0x00000070
#define study_MRSRB_CL_1 0x00000000
#define study_MRSRB_CL_2 0x00000020
#define study_MRSRB_CL_3 0x00000030
//-----------------------------------------------------------------------------
// UART
#define study_UART0_BASE (study_REG_BASE + 0x100000)
#define study_UART1_BASE (study_REG_BASE + 0x104000)
#define study_UART_LCON 0x0000
#define study_UART_CON 0x0004
#define study_UART_FCON 0x0008
#define study_UART_MCON 0x000c
#define study_UART_TRSTAT 0x0010
#define study_UART_ERSTAT 0x0014
#define study_UART_FSTAT 0x0018
#define study_UART_MSTAT 0x001c
// little endian
#define study_UART_TXBUF 0x0020
#define study_UART_RXBUF 0x0024
// big endian
//#define study_UART_TXBUF 0x0023
//#define study_UART_RXBUF 0x0027
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