📄 define.h
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#define TRUE 1
#define FALSE 0
#define MEMORY_BASE 0x2000
#define MARK XBYTE[0xf8]
//display current run status,
//0:cool start
//1:hot start
//0x55: nor flash interface
//0xaa: card program need new program to load into memory
#define BOOT_NUMBER XBYTE[0xf9]
#define SYS_UPDATA XBYTE[0xFE]
#define DIRECT_RUN_UD XBYTE[0XFF]
//FOR record repeat boot number,if this number>5,reboot fail,
#define READ_LEN XBYTE[MEMORY_BASE]
//new program length need read into memory.
#define CARD_NUMBER XBYTE[MEMORY_BASE+1]
//current using card number,if for load new program,then point out which card
#define READ_BLOCK_H XBYTE[MEMORY_BASE+2]
#define READ_BLOCK_M XBYTE[MEMORY_BASE+3]
#define READ_BLOCK_L XBYTE[MEMORY_BASE+4]
#define READ_PAGE_ADDR XBYTE[MEMORY_BASE+5]
//THIS three bytes used to define address for read into memory of new program
#define B_TO_P_NUMBER XBYTE[MEMORY_BASE+6]
//this card's one block eque any page
#define CARD_BASE MEMORY_BASE+0x10
//used storage have been found all card's number and type,and its tail is 0xff
#define MCU_IO_BASE 0
/*mcu io base*/
#define IDMA_BASE 0x0c00
/*idma io base*/
#define MCU_IER_L MCU_IO_BASE + 0
//mcu interrupt enable register
#define MCU_IER_H MCU_IO_BASE + 1
#define MCU_ISR MCU_IO_BASE + 2
//mcu interrupt status register
#define CLKGATE_CTRL_L MCU_IO_BASE + 4
//clock gate control register
#define CLKGATE_CTRL_M MCU_IO_BASE + 5
//clock gate control register
#define CLKGATE_CTRL_H MCU_IO_BASE + 6
//clock gate control register
#define CLK_SEL MCU_IO_BASE + 8
//clock select register
#define POWER_CTRL MCU_IO_BASE + 9
//card power control register
#define SYS_CFG MCU_IO_BASE + 0xa
//system control register
#define BUF_CTRL MCU_IO_BASE + 0xd
//double buffer control register
#define BUFA_CTRL MCU_IO_BASE + 0xe
//buffer A control & status register
#define BUFB_CTRL MCU_IO_BASE + 0xf
//buffer B control & status register
#define BIST_EN MCU_IO_BASE + 0x10
//ram bist enable register
#define BIST_MODE MCU_IO_BASE + 0x11
//ram bist mode register
#define BIST_DONE MCU_IO_BASE + 0x12
//ram bist done register
#define BIST_FAIL MCU_IO_BASE + 0x13
//ram bist fail flag register
#define DSP_CTRL MCU_IO_BASE + 0x30
//dsp control register
#define DSP_FLG MCU_IO_BASE + 0x32
//dsp flag output to mcu
#define INT_OUT MCU_IO_BASE + 0x33
//dsp input setting to dsp pin
#define SDRAM_C_S MCU_IO_BASE + 0x40
//sdram command ,status register
#define SDRAM_RATE MCU_IO_BASE + 0x41
//sdram refresh rate register
#define SDRAM_ADDR MCU_IO_BASE + 0x42
//sdram address split mode register
#define SDRAM_TIMING MCU_IO_BASE + 0x44
//sdram timming parameter register
#define SDRAM_MODE MCU_IO_BASE + 0x46
//sdram mode set register
#define SDRAM_AUTO_LEN MCU_IO_BASE + 0x48
//sdram auto refresh burst length register
#define SDRAM_STATUS MCU_IO_BASE + 0x49
//sdram self refresh status register
#define SDRAM_CFG MCU_IO_BASE + 0x4a
//sdram enhance config register
#define AUD_DMA_BASE 0x60
//audio dma base
#define AUD_DMA_LEN 0x64
//audio dma length register
#define AUDTOMEM_ADDR 0x68
//audio access sdram address
#define EXT_GPIO_STATUS MCU_IO_BASE + 0x70
//extend gpio status register
#define EXT_GPIO_OUT MCU_IO_BASE + 0x76
//extend gpio output register
#define EXT_GPIO_OUTCTL MCU_IO_BASE + 0x7c
//extend gpio output control register
#define EXT_GPIO_PADCTL MCU_IO_BASE + 0x82
//extend gpio pad select control register
#define SYS_TEST 0xf0
//system test register
#define IDMA_DATA IDMA_BASE + 0
//dsp idma interface data register
#define IDMA_ADDR IDMA_BASE + 2
//dsp idma interface address register
#define IDMA_CTRL IDMA_BASE + 8
//dsp idma interface control register
#define IDMA_STATUS IDMA_BASE + 9
//dsp idma interface status register
#define IDMA_BUF_ADDR IDMA_BASE + 0xa
//dsp idma buffer address register
#define IDMA_BLK_SIZE IDMA_BASE + 0xc
//idma transaction length
#define LCD_DATA 0x400
#define LCD_CMDL 0x400
#define LCD_CMDH 0x401
#define LCD_STATUS 0x403
#define SMC_DATA 0x600
#define SMC_CMD 0x601
#define SMC_ADDR 0x602
#define SMC_MADDR 0x603
#define SMC_CTL 0x604
#define SMC_STATUS 0x605
#define SMC_IER 0x606
#define SMC_ISR 0x607
#define SMC_DCTRL_L 0x608
#define SMC_DCTRL_H 0x609
#define MEM_ADDR 0x0d00
//mcu access sdram address
#define MEM_DATA 0x0d04
//mcu access sdram data register
#define MEM_CTRL 0x0d07
//mcu access sdram control register
#define HOBOX_BASE 0x100
//mcu to dsp mail box
#define HIBOX_BASE 0x200
//dsp to mcu mail box
#define CMD_MODLE 0x40
#define DATA_MODLE 0x42
#define STATUS_MODLE 0x41
#define MCU_CLK_2
#ifdef MCU_CLK_00
#define MCU_CLK 0
//mcu clk set to 1.536M
#endif
#ifdef MCU_CLK_01
#define MCU_CLK 1
//mcu clk set to 6.144M
#endif
#ifdef MCU_CLK_10
#define MCU_CLK 2
//mcu clk set to 24.576M
#endif
#ifdef MCU_CLK_11
#define MCU_CLK 3
#endif
//mcu clk set to 12.288M
#ifdef MCU_CLK_2
#define MCU_CLK 6
//mcu clk set to 12.288M,DSP 48m
#endif
#define HIBOX0 0x200
#define HIBOX1 0x201
#define HIBOX2 0x202
#define HIBOX3 0x203
#define HOBOX0 0x100
#define HOBOX1 0x101
#define HOBOX2 0x102
#define HOBOX3 0x103
#define RECORD 0X1101
#define PLAY 0x1100
#define PAUSE 0x1200
#define STOP 0XAA00
#define EQ_NONE 0X2200
#define EQ_JAZZ 0X2201
#define EQ_POP 0X2202
#define EQ_CLAS 0X2203
#define EQ_ROCK 0X2204
#define READ_HOUR 0X3300
#define READ_MIN 0X4400
#define READ_SEC 0X5500
#define READ_SR 0X6600
#define FF 0X7700
#define FB 0X7701
#define BUF0_OK 0X8800
#define BUF1_OK 0X8801
#define DSP_PWD 0XFF00
#define SET_HOUR 0X2000
#define SET_MIN 0X2100
#define SET_SEC 0X2200
#define SET_SR 0X6000
#define SET_SPEED 0X7000
//=============================================================================
#define MCU_IER 0x00
//#define MCU_ISR 0x02
#define CLKGATE_CTRL 0x04
//#define CLK_SEL 0x08
//#define POWER_CTRL 0x09
//#define SYS_CFG 0x0A
//#define BUF_CTRL 0x0D
//#define BUFA_CTRL 0x0E
//#define BUFB_CTRL 0x0F
//#define BIST_EN 0x10
//#define BIST_MODE 0x11
//#define BIST_DONE 0x12
#define BIST_STATUS 0x13
//#define DSP_CTRL 0x30
//#define DSP_FLG 0x32
#define IN_OUT 0x33
#define MEM_CMD 0x40
#define MEM_REFRATE 0x41
#define MEM_SPLIT 0x42
#define MEM_PAR 0x44
#define MEM_MODE 0x46
#define MEM_AREF 0x48
#define MEM_SREF 0x49
#define MEM_CFG 0x4A
#define AUD_DMA_BASE 0x60
#define AUD_DMA_LEN 0x64
#define AUD2MEM_ADDR 0x68
#define EGPIO_IN 0x70
#define EGPIO_OUT 0x76
#define EGPIO_CTRL 0x7C
#define EGPIO_SEL 0x82
//#define SYS_TEST 0xF0
#define MCU_UTIL0 0xF8
#define MCU_UTIL1 0xFC
#define USB_BASE 0x300
#define LCD_BASE 0x400
#define I2C_BASE 0x500
#define SMC_BASE 0x600
#define IRC_BASE 0x700
#define CD_BASE 0x800
#define SUBQ_BASE 0x880
#define SPI_BASE 0x900
#define SD_BASE 0xA00
#define MS_BASE 0xB00
//#define IDMA_BASE 0xC00
#define MEM_BASE 0xD00
#define UART_BASE 0xE00
#define CF_BASE 0xF00
#define FBUF_BASE 0x1000
#define SRAM_BASE 0x6000
//define interrupt status bit
#define COMM_INT 0X01
#define DATA_INT 0X08
#define IDMA_INT 0X02
#define FLASH_INT 0X02
#define IntfRw (XBYTE[SYS_CFG] & 0Xf0)
#define SdramIntf (XBYTE[SYS_CFG] = IntfRw | 7)
#define MsIntf (XBYTE[SYS_CFG] = IntfRw | 1)
#define SmcIntf (XBYTE[SYS_CFG] = IntfRw)
#define MmcIntf (XBYTE[SYS_CFG] = IntfRw | 2)
#define SdIntf (XBYTE[SYS_CFG] = IntfRw | 2)
#define Sdram_Rw (XBYTE[SYS_CFG] = IntfRw | 7)
#define McuRw (XBYTE[BUFA_CTRL] = 0)
#define MemoryRw (XBYTE[BUFA_CTRL] = 1)
#define UsbRw (XBYTE[BUFA_CTRL] = 2)
#define DspRw (XBYTE[BUFA_CTRL] = 3)
#define Smc_Disable (XBYTE[SMC_CTL] = XBYTE[SMC_CTL] &0x7f)
#define Read(Addr) XBYTE[Addr]
#define Write(Addr,Y) XBYTE[Addr] = Y
#define IDMA_BANK_MASK 0xc000
#define IDMA_BANK_PM 0x0000
#define IDMA_BANK_DMX 0x4000
#define IDMA_BANK_DMY 0x8000
#define TIME_HOUR 0X3300
#define TIME_MINUTE 0X4400
#define TIME_SECOND 0X5500
struct DisplayFormat
{
unsigned char Mode; //1:for all lcd display
//2:for china display
//3:for english display
unsigned char DisplayFg; //bit 0-- 0:double line,1: single line
//bit 1-- 0:bit0 valid ,1:order display,bit0 invalid
//bit 2-- 0:none slide,1:slide
//bit 3-- 0:normal display, 1:converse display
//bit 7-- 0:not display,1:need display
unsigned char LineNumber; //line number,0~4
unsigned char *DisplayBuff; //display buffer pointer
unsigned char LcdStartAddr; //LCD display from
unsigned short LcdLength; //LCD display length
unsigned char SlideStart; //slide start address in display buffer
unsigned char SlideEnd; //slide end address in display
unsigned char SlideCount; //slide counter
};
struct DiskFormat
{
unsigned short BytePerSector; //byte per sector
unsigned char SectorPerCluster; //sector per cluster
char NumFats; //fats number
unsigned short RootDirEntry; //root director entry
unsigned long TotolSector; //torol sector
char MediaId;
unsigned short NumFatSector; //fat list's sector number
char FatFormat; //disk format 0x12,0x16,0x32
};
struct LogicAddress
{
unsigned char Segment;
unsigned short Cluster;
unsigned short Sector;
unsigned short Number;
};
struct AbsAddress
{
unsigned char Disk;
unsigned short Block;
unsigned char Page;
unsigned short Number;
};
struct PlayList
{
unsigned char Index; //mp3 file index
struct LogicAddress FctAddr; //Fct Address
struct LogicAddress FatAddr; //Fat Address
};
struct TimeFormat
{
unsigned short Year;
unsigned char Month;
unsigned char Date;
unsigned char Hour;
unsigned char Minuts;
};
struct File
{
unsigned int FirstClustor;
unsigned int CurrentClustor;
unsigned int FileSize0;
unsigned int FileSize1;
unsigned long Pointer;
};
struct FileFormat
{
char *FileName;
unsigned long FileLen;
struct TimeFormat Time;
char Attrib;
struct PlayList Address;
};
struct DspCommand {
unsigned char Cmd0, Cmd1, Cmd2;
};
struct LogicAddStack
{ unsigned int Cluster;
unsigned int Sector;
unsigned char Number;
};
//=============================================================================
struct t2time
{ unsigned char Hour;
unsigned char Minute;
unsigned char Second;
};
//=============================================================================
#define DEBUG
#define UDB
//=============================================================================
//(2048-256)*32 last 256block=4M put record file
#define RECORD_POFFSET 57344
#define RECORD_BOFFSET 1792
#define RECORD_LENGTH 300
#define RECORD_MAXLEN 8192
#define UDISK_BOFFSET 100
#define FONT_BOFFSET UDISK_BOFFSET-20
#define CFONT_BOFFSET FONT_BOFFSET+0
#define EFONT_BOFFSET FONT_BOFFSET+16
#define PICON_BOFFSET FONT_BOFFSET+17
#define BICON_BOFFSET FONT_BOFFSET+18
/*
#define CFONT_POFFSET CFONT_BOFFSET*32
#define EFONT_POFFSET EFONT_BOFFSET*32
#define PICON_POFFSET PICON_BOFFSET*32
#define BICON_POFFSET BICON_BOFFSET*32
*/
#define CFONT_POFFSET 2560
#define EFONT_POFFSET 3072
#define PICON_POFFSET 3104
#define BICON_POFFSET 3136
#define NUM0_OFFSET 48
#define CLUSTER_WIDTH 512
//=============================================================================
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