common.h

飞利浦公司usb2.0芯片isp1581的通用驱动代码

/*
   //*************************************************************************
   //
   //                  P H I L I P S   P R O P R I E T A R Y
   //
   //           COPYRIGHT (c)   2000 BY PHILIPS SINGAPORE.
   //                     --  ALL RIGHTS RESERVED  --
   //
   // Project:		ISP1581 EVA board
   // File Name:	common.h
   // Author:		Qian Jiang
   // Created:		Sept. 1, 2000
   // Modified:
   // Revision:		0.0
   //
   //*************************************************************************
*/
#ifndef __COMMON_H__
#define __COMMON_H__

#include "BasicTyp.h"
/*
   //*************************************************************************
   // macros
   //*************************************************************************
*/
#define SWAP(x)   (x)

#define MSB(x)    (((x) >> 8) & 0xFF)
#define LSB(x)    ((x) & 0xFF)

#define RaiseIRQL() disable()
#define LowerIRQL() enable()  


#define NULL_LENGTH 0xff
/*
   //*************************************************************************
   // structure and union definitions
   //*************************************************************************
*/
typedef union _ISP1581FLAGS {
	struct _ISP1581FSM_FLAGS
	{

// Byte 0
		IRQL_1 UCHAR    reserved1			: 1;
		IRQL_1 UCHAR    suspend				: 1;

		IRQL_0 UCHAR    configuration		: 1;
		IRQL_0 UCHAR    remote_wakeup		: 1;

		IRQL_0 UCHAR    testmodeen			: 1;
		IRQL_0 UCHAR    testmode			: 3;
// Byte 1
		IRQL_1 UCHAR    DCP_state			: 4;    /* Default Control Pipe FSM state */
		IRQL_1 UCHAR    CONTROL_HANDLE_DONE	: 1;    /* Access Data via DCP from/to IO data port or Memory*/
		//true iso
		IRQL_1 UCHAR    ISO_state			: 3;
		IRQL_1 UCHAR    ISO_CONFIG			: 1;

// Byte 2
		IRQL_1 UCHAR	setup_dma			: 1;
		IRQL_1 UCHAR	dma_endpoint		: 4;
		IRQL_1 UCHAR	dma_state			: 2;
// Byte 3
		IRQL_1 UCHAR    ConnectSpeed		: 1;
//		IRQL_0 UCHAR    Reserved20			: 1;


		IRQL_1 UCHAR    verbose				: 1;    /* Debug info*/
		IRQL_1 UCHAR    timer				: 1;
		IRQL_1 UCHAR    dbg					: 1;
		// patches
		IRQL_1 UCHAR    Vendor_CMD			: 1;
		IRQL_1 UCHAR	BULKIN_EP1_STALL	: 1;
		IRQL_1 UCHAR    At_IRQL1			: 1;
		IRQL_1 UCHAR    FREE_DMA_CHANNEL	: 1;
//		IRQL_1 UCHAR    Reserved2			: 1;
	} bits;

	ULONG value;

} ISP1581FLAGS;

typedef struct _device_request{
	UCHAR bmRequestType;
	UCHAR bRequest;
	USHORT wValue;
	USHORT wIndex;
	USHORT wLength;
} DEVICE_REQUEST;

// ******************************************************************************

typedef struct _IO_REQUEST {
	unsigned short	uAddressL;
	unsigned char	bAddressH;
	unsigned short	uSize;
	unsigned char	bCommand;
} IO_REQUEST, *PIO_REQUEST;

//*******************************************************************************


/*
// MAX_CONTROLDATA_SIZE is between ADSC command and 50ms*384Bytes/ms=18KBytes
// MaxSize for RBC command is 16 Bytes
*/
#define MAX_CONTROLDATA_SIZE	16
typedef struct _CONTROL_XFER
{
	IRQL_1 BOOLEAN          Abort;      /*Indicate this transfer shall be aborted ASAP*/
	IRQL_1 DEVICE_REQUEST   DeviceRequest;
	IRQL_1 USHORT  		    wLength;
	IRQL_1 USHORT  		    wCount;
	IRQL_1 ADDRESS          Addr;
	IRQL_1 UCHAR            dataBuffer[MAX_CONTROLDATA_SIZE];

/*
//    PCONTROL_XFER           NextXfer;
*/

} CONTROL_XFER, * PCONTROL_XFER;



/*
//*************************************************************************
// basic FSM state
//*************************************************************************
*/

#define USBFSM_ATTACHED             0
#define USBFSM_POWRED               1
#define USBFSM_DEFAULT              2
#define USBFSM_ADDRESS              3
#define USBFSM_CONFIGURED           4
#define USBFSM_SUSPENDED            5

#define USBFSM_RESET                USBFSM_DEFAULT


/*
// FSM for Default Control Pipe

Control out
with data phase
setup -> setup process -> data out -> control out done -> requeset process -> countrol write handshake -> idle
without data phase
setup -> setup process -> requeset process -> countrol write handshake -> idle

Control in
setup -> setup process -> requeset process (data sent to host) -> data in (multiple data pkt to host) -> countrol read handshake -> idle

in any case of unable to process host command, stall will be issued, and the state is in stall, in consequent in or out transfer
stall is continiued untill be cleared by a setup from host;
*/
#define USBFSM4DCP_IDLE						0x0
#define USBFSM4DCP_SETUPPROC				0x1
#define USBFSM4DCP_REQUESTPROC				0x2
#define USBFSM4DCP_REQUESTPROC1				0x3 // not used
#define USBFSM4DCP_DATAIN					0x4
#define USBFSM4DCP_DATAOUT					0x5
#define USBFSM4DCP_CONTROLOUTDONE			0x6
#define USBFSM4DCP_CONTROLREADHANDSHAKE		0x7
#define USBFSM4DCP_CONTROLWRITEHANDSHAKE	0x8
#define USBFSM4DCP_STALL					0xa

//USB1.1 or 2.0 connection indication:
//#define LowSpeed 0x00
#define HighSpeed 0x01
#define FullSpeed 0x00

#endif