📄 isp1581.h
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/*
//*************************************************************************
//
// P H I L I P S P R O P R I E T A R Y
//
// COPYRIGHT (c) 2000 BY PHILIPS SINGAPORE.
// -- ALL RIGHTS RESERVED --
//
// Project: ISP1581 EVA board
// File Name: ISP1581.H
// Author: Qian Jiang
// Created: Sept. 1, 2000
// Modified:
// Revision: 0.0
//
//*************************************************************************
*/
#ifndef __ISP1581_H__
#define __ISP1581_H__
//#include "BasicTyp.h"
#define rega_addren 0xff00
#define rega_epmaxsize 0xff04
#define rega_eptype 0xff08
#define rega_mode 0xff0c
#define rega_intcfg 0xff10
#define rega_intmask_low 0xff14
#define rega_intmask_high 0xff16
#define rega_interrupt_low 0xff18
#define rega_interrupt_high 0xff1a
#define rega_dcount 0xff1c
#define rega_dport 0xff20
#define rega_shtpkt 0xff24
#define rega_epctlfc 0xff28
#define rega_epindex 0xff2c
#define rega_dmacmd 0xff30
#define rega_dmacount 0xff34
#define rega_dmacfg 0xff38
#define rega_dmahdcfg 0xff3c
#define rega_dmast 0xff60
#define rega_task1f0 0xff40
#define rega_task1f1 0xff48
#define rega_task1f2 0xff48
#define rega_task1f3 0xff4a
#define rega_task1f4 0xff4a
#define rega_task1f5 0xff4c
#define rega_task1f6 0xff4c
#define rega_task1f7 0xff44
#define rega_task3f6 0xff4e
#define rega_task3f7 0xff4e
#define rega_dmaint 0xff50
#define rega_dmaintmask 0xff54
#define rega_dmaep 0xff58
#define rega_dmastate 0xff5c
#define rega_chipid 0xff70
#define rega_framenumber 0xff74
#define rega_scratch 0xff78
#define rega_unlock 0xff7c
#define rega_testmode 0xff84
#define addren_enable 0x80
#define addren_addrmask 0x7f
#define int_busreset 0x0001
#define int_sof 0x0002
#define int_psof 0x0004
#define int_susp 0x0008
#define int_resume 0x0010
#define int_hs_stat 0x0020
#define int_dma 0x0040
#define int_ep0set 0x0100
#define int_ep0rx 0x0400
#define int_ep0tx 0x0800
#define int_ep1rx 0x1000
#define int_ep1tx 0x2000
#define int_ep2rx 0x4000
#define int_ep2tx 0x8000
#define int_ep3rx 0x0001
#define int_ep3tx 0x0002
#define int_ep4rx 0x0004
#define int_ep4tx 0x0008
#define int_ep5rx 0x0010
#define int_ep5tx 0x0020
#define int_ep6rx 0x0040
#define int_ep6tx 0x0080
#define int_ep7rx 0x0100
#define int_ep7tx 0x0200
#define eptype_control 0x00
#define eptype_iso 0x01
#define eptype_bulk 0x02
#define eptype_int 0x03
#define eptype_doublebuf 0x04
#define eptype_enable 0x08
#define eptype_noempkt 0x10
#define mode_softct 0x01
#define mode_pwroff 0x02
#define mode_wkupcs 0x04
#define mode_glintena 0x08
#define mode_reset 0x10
#define mode_gosusp 0x20
#define mode_sndrsu 0x40
#define mode_clkaon 0x80
#define intcfg_cdbgmod_asn 0x00
#define intcfg_cdbgmod_as 0x40
#define intcfg_cdbgmod_as1n 0x80
#define intcfg_ddbgmodin_an 0x00
#define intcfg_ddbgmodin_a 0x10
#define intcfg_ddbgmodin_a1n 0x30
#define intcfg_ddbgmodout_asyn 0x00
#define intcfg_ddbgmodout_asy 0x04
#define intcfg_ddbgmodout_asy1n 0x08
#define intcfg_edgetrig 0x02
#define intcfg_polh 0x01
#define EPINDEX4CONTROL_SETUP 0x20
#define EPINDEX4CONTROL_OUT 0x00
#define EPINDEX4CONTROL_IN 0x01
#define EPINDEX4EP01OUT 0x02
#define EPINDEX4EP01IN 0x03
#define EPINDEX4EP02OUT 0x04
#define EPINDEX4EP02IN 0x05
#define EPINDEX4EP03OUT 0x06
#define EPINDEX4EP03IN 0x07
#define EPINDEX4EP04OUT 0x08
#define EPINDEX4EP04IN 0x09
#define EPINDEX4EP05OUT 0x0A
#define EPINDEX4EP05IN 0x0B
#define EPINDEX4EP06OUT 0x0C
#define EPINDEX4EP06IN 0x0D
#define EPINDEX4EP07OUT 0x0E
#define EPINDEX4EP07IN 0x0F
#define epctlfc_stall 0x01
#define epctlfc_status 0x02
#define epctlfc_venp 0x08
#define epctlfc_clbuf 0x10
#define maxepsize_0 0x0000
#define maxepsize_1 0x0001
#define maxepsize_2 0x0002
#define maxepsize_4 0x0004
#define maxepsize_8 0x0008
#define maxepsize_16 0x0010
#define maxepsize_32 0x0020
#define maxepsize_64 0x0040
#define maxepsize_128 0x0080
#define maxepsize_256 0x0100
#define maxepsize_512 0x0200
#define maxepsize_956 0x03bc
#define maxepsize_1024 0x0400
#define NTRAN_1 0x0000
#define NTRAN_2 0x0800
#define NTRAN_3 0x1800
#define shtpkt0out 0x0100
#define shtpkt1out 0x0200
#define shtpkt2out 0x0400
#define shtpkt3out 0x0800
#define shtpkt4out 0x1000
#define shtpkt5out 0x2000
#define shtpkt6out 0x4000
#define shtpkt7out 0x8000
#define chipid 0x1581
#define chiprev 0x0010
#define unlockcode 0xaa37
#define testmode_se0nak 0x0001
#define testmode_jstate 0x0002
#define testmode_kstate 0x0004
#define testmode_prbs 0x0008
#define testmode_forcefs 0x0010
#define testmode_lpbk 0x0020
#define testmode_phytest 0x0040
#define testmode_forcehs 0x0080
#define dmacmd_gdmaread 0x00
#define dmacmd_gdmawrite 0x01
#define dmacmd_udmaread 0x02
#define dmacmd_udmawrite 0x03
#define dmacmd_pioread 0x04
#define dmacmd_piowrite 0x05
#define dmacmd_mdmaread 0x06
#define dmacmd_mdmawrite 0x07
#define dmacmd_piowritecomplete 0x07
#define dmacmd_pioreadcomplete 0x09
#define dmacmd_read1f0 0x0a
#define dmacmd_pollbsy 0x0b
#define dmacmd_readalltask 0x0c
#define dmacmd_validatebuffer 0x0e
#define dmacmd_clearbuffer 0x0f
#define dmacmd_restart 0x10
#define dmacmd_reset 0x11
#define dmacfg_width16 0x0001
#define dmacfg_width8 0x0000
#define dmacfg_modediorw 0x0000
#define dmacfg_modediorack 0x0004
#define dmacfg_modedack 0x0008
#define dmacfg_burstdmd 0x0000
#define dmacfg_burst0 0x0000
#define dmacfg_burst1 0x0010
#define dmacfg_burst2 0x0020
#define dmacfg_burst4 0x0030
#define dmacfg_burst8 0x0040
#define dmacfg_burst12 0x0050
#define dmacfg_burst16 0x0060
#define dmacfg_burst32 0x0070
#define dmacfg_disablecounter 0x0080
#define dmacfg_pio0 0x0000
#define dmacfg_pio1 0x0100
#define dmacfg_pio2 0x0200
#define dmacfg_pio3 0x0300
#define dmacfg_pio4 0x0400
#define dmacfg_dma0 0x0000
#define dmacfg_dma1 0x0800
#define dmacfg_dma2 0x1000
#define dmacfg_dma3 0x1800
#define dmacfg_atamode0 0x0000
#define dmacfg_atamode1 0x2000
#define dmacfg_ignorerdy 0x4000
#define dmahd_readpolh 0x01
#define dmahd_writepolh 0x02
#define dmahd_dreqpolh 0x04
#define dmahd_dackpolh 0x08
#define dmahd_master 0x10
#define dmahd_eotpolh 0x20
#define dmahd_endianbig 0x40
#define dmaint_autodone 0x0001
#define dmaint_cmddone 0x0002
#define dmaint_taskdone 0x0004
#define dmaint_bsydonw 0x0008
#define dmaint_1f0full 0x0010
#define dmaint_1f0rdempty 0x0020
#define dmaint_1f0wrfull 0x0040
#define dmaint_1f0wrempty 0x0080
#define dmaint_xferok 0x0100
#define dmaint_intpending 0x0200
#define dmaint_intereot 0x0400
#define dmaint_extereot 0x0800
#define dmaint_oddint 0x1000
// dmaintmask shares the same bit definition as dma interrupt reason register;
#define EP0_FIFO_SIZE maxepsize_64
#define EP0_PACKET_SIZE maxepsize_64
#define ctlportb_hdreset 0x01
// Member Functions
void ISP1581_ResetDevice(void);
unsigned short ISP1581_ReadChipID(void);
USHORT ISP1581_GetDataFromChipRam(void);
void ISP1581_SetDataToChipRam(USHORT wData);
void ISP1581_UnlockDevice(void);
UCHAR ISP1581_GetIntConfig(void);
void ISP1581_SetIntConfig(UCHAR bMode);
UCHAR ISP1581_GetMode(void);
void ISP1581_SetMode(UCHAR bMode);
void ISP1581_SetEPIndex(UCHAR bEPIndex);
UCHAR ISP1581_GetEPIndex(void);
void ISP1581_ConfigEndpoint(void);
void ISP1581_SetEPMAXSize(unsigned char bEPIndex, unsigned short epmaxsize);
unsigned short ISP1581_GetEPMAXSize(unsigned char bEPIndex);
UCHAR ISP1581_GetEndpointConfig(UCHAR bEPIndex);
void ISP1581_SetEndpointConfig(UCHAR bEPIndex, UCHAR bEPConfig);
void ISP1581_SetEndpointStatus(UCHAR bEPIndex, UCHAR bStalled);
UCHAR ISP1581_GetEndpointStatus(UCHAR bEPIndex);
USHORT ISP1581_GetDMAConfig(void);
void ISP1581_SetDMAConfig(USHORT wDMAConfig);
USHORT ISP1581_GetDMACounterLow(void);
void ISP1581_SetDMACounterLow(USHORT wDMACounter);
USHORT ISP1581_GetDMACounterHigh(void);
void ISP1581_SetDMACounterHigh(USHORT wDMACounter);
void ISP1581_SetAddressEnable(UCHAR bAddress, UCHAR bEnable);
UCHAR ISP1581_GetAddress(void);
void ISP1581_SendResume(void);
void ISP1581_GoSuspend(void);
void ISP1581_SoftConnect(UCHAR bEnable);
void ISP1581_SetIntEnableLow(USHORT wIntEn);
void ISP1581_SetIntEnableHigh(USHORT wIntEn);
USHORT ISP1581_GetIntEnableLow(void);
USHORT ISP1581_GetIntEnableHigh(void);
USHORT ISP1581_ReadInterruptRegisterLow(void);
USHORT ISP1581_ReadInterruptRegisterHigh(void);
void ISP1581_IntClearl(USHORT wIntlow);
void ISP1581_IntClearh(USHORT wInthigh);
void ISP1581_ClearBuffer(UCHAR bEPIndex);
void ISP1581_ValidBuffer(UCHAR bEPIndex);
void ISP1581_ControlWriteHandshake(void);
void ISP1581_ControlReadHandshake(void);
USHORT ISP1581_SHORTPKT(void);
USHORT ISP1581_GetPktLength(void);
USHORT ISP1581_ReadControlEndpoint(UCHAR * buf, unsigned short len);
USHORT ISP1581_WriteControlEndpoint(UCHAR * buf, USHORT len);
//for loop back
void ISP1581_WriteBulkEndpoint(UCHAR bEPIndex, unsigned short far * buf, USHORT len);
USHORT ISP1581_ReadBulkEndpoint(UCHAR bEPIndex, unsigned short far * buf, USHORT len);
void ISP1581_WriteISOEndpoint(UCHAR bEPIndex, unsigned short far * buf, USHORT len);
USHORT ISP1581_ReadISOEndpoint(UCHAR bEPIndex, unsigned short far * buf);
USHORT ISP1581_ReadCurrentFrameNumber(void);
void ISP1581_StallEP0InControlWrite(void);
void ISP1581_StallEP0InControlRead(void);
void ISP1581_UnconfigDevice(void);
void ISP1581_ConfigDevice(void);
void ISP1581_RegAccess(void);
void ISP1581_SetDCount(unsigned short dcount);
unsigned short ISP1581_GetDCount(void);
USHORT ISP1581_GetDMAStrobeTiming(void);
USHORT ISP1581_GetDMAInt(void);
void ISP1581_SetDMAInt(USHORT dma_int);
void ISP1581_SetDMAIntMask(unsigned short dmaintmask);
unsigned short ISP1581_GetDMAIntMask(void);
void ISP1581_SetDMAEP(unsigned char dmaep);
unsigned char ISP1581_GetDMAEP(void);
void ISP1581_SetTestMode(unsigned char testmode);
unsigned char ISP1581_GetTestMode(void);
void ISP1581_SetDMACMD(unsigned bCMD);
USHORT ISP1581_GetDMAState(void);
void ISP1581_SetTaskFile(USHORT taskfile, UCHAR taskfile_value);
UCHAR ISP1581_GetTaskFile(USHORT taskfile);
void HARDWARE_RESET(void);
void interrupt_enable(void);
void ISP1581_Initiate(void);
#endif
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