main.c

BF533的程序

/*****************************************************************************************/
// Name: 	BF532-based EZ-KIT PAL Camera Capture program								//
/*****************************************************************************************

Project Name:	PAL_Capture.dpj

Version:		1.0

Author:			Tan Tien Peng Cyril
Designation:	Engineer

Software:       VisualDSP++3.5

Hardware:		ADSP BF532-based EZ-KIT Board Rev 1.7
				CCD Camera

Special Connections:  	
				Connect a CVBS video source to the right bottom video jack "AVIN1"
                change switch #6 of SW3 to on of the ADSP-BF532-based EZ-KIT Lite.
				
Description:	This program performs image processing on an image captured using
				PAL-based CCD camera. However, image processing portion has been
				eliminated in this program for image capturing demonstration purposes.
				
				Pls note that this program is edited from the ADI Video Input example!

Operation:		After reset, the ADV7183 is configured to output digital
				video data in ITU656 mode 8 bits wide. Additionally, The DSP is 
				configured to receive video data in ITU-656 format via the PPI Interface.
				The DMA channel 0 is dedicated to transfer the data to the 
				external SDRAM immediately (Address 0x0). 
				
******************************************************************************************/

#include "cplb.h"//cache
#include <cdefBF533.h>		//BF533 Register Pointer Definition
#include <stdio.h>
#include <sys\exception.h>		//Interrupt Handling Header
#include "flashsetup.h"


//int __cplb_ctrl =CPLB_ENABLE_ICPLBS | CPLB_ENABLE_ICACHE|
//CPLB_ENABLE_DCPLBS|CPLB_ENABLE_DCACHE|CPLB_ENABLE_DCACHE2;//cache

// Sets up here all Prototype Functions 
void Init_EBIU(void);
void Init_Flash(void);
void Init_ADV(void);
void Init_Interrupts(void);
void Init_SDRAM(void);
void Init_DMA(void);
void Init_PPI(void);
void Init_PLL(void);
void Init_UART(void);
void convert(void);
void cacheinit();


volatile int done;



	
void main()
{  int i6,count=0,c1=0;
    unsigned short int *Ptr,*tmp, *Dst, *Cb, *Cr;

	unsigned char RXD = 0;
	unsigned char *a;
	unsigned char b[100];
	a=(unsigned char*)0x0;
	int i;
	int mm=0;
	done=0;
	//	Setup Blackfin and ADV7183 video decoder;
	/////////////////////////////////////////////////////	
	Init_PLL();
	Init_EBIU();		//	Async Memory Interface Setup
	Init_UART();
	
	Init_Flash();		//	Flash Setup to config the flash GPIOs
	Init_ADV();			//	Link the ADV7183 clock to the PPI and ADV7183 reset
	
	Init_Interrupts();	//	Enter an interrupt subroutine after DMA has been finished
	cacheinit();

	Init_SDRAM();		//	SDRAM Setup to store the video image

////	Init_Flash();		//	Flash Setup to config the flash GPIOs
////	Init_ADV();			//	Link the ADV7183 clock to the PPI and ADV7183 reset
//	for (i = 0; i < 0x011FFFFF; i++);	//	Gives the ADV7183 to lock after reset

///////////////////////////////////////////////////
Ptr = (unsigned short int *) 0x100000;
Dst= (unsigned short int *)  0x200000;
Ptr[0]=0x5555;
Ptr[1]=0xaaaa;
for(i=2;i<52;i++)
{
	Ptr[i]=i-2;
}
for(i=2;i<52;i++)
{
	Dst[i-2]=Ptr[i];
}
while(1)
{count++;
	if(Ptr[0]==0x5555)
	{
		////////////////////////////控制灯得开关
	*pFIO_DIR|=0x10;
	
	*pFIO_FLAG_D|=0x10;
	for(i6=0;i6<5000000;i6++);
	*pFIO_FLAG_D&=0xffef;
	for(i6=0;i6<5000000;i6++);

	}
	else
	{
		c1++;
	}
	
	
}


////////////////////////////控制灯得开关
	*pFIO_DIR|=0x10;
	
	*pFIO_FLAG_D|=0x10;
	for(i6=0;i6<10000000;i6++);
	*pFIO_FLAG_D&=0xffef;


}//end main

void convert()
{

	volatile unsigned short us_MemDMA0_Src0_Descriptor1[9];
    volatile unsigned short us_MemDMA0_Src1_Descriptor1[9];
    volatile unsigned short us_MemDMA0_Src2_Descriptor1[9];
    
    volatile unsigned short us_MemDMA0_Dst0_Descriptor1[9];
    volatile unsigned short us_MemDMA0_Dst1_Descriptor1[9];
    volatile unsigned short us_MemDMA0_Dst2_Descriptor1[9];
    volatile unsigned short us_MemDMA0_END1[9];
    volatile unsigned char *Ptr, *Y, *Cb, *Cr;
    Ptr = (unsigned char *) 0x00;
	Y = (unsigned char *) 0x0012FC00;
	Cb = (unsigned char *) 0x00195000;
	Cr = (unsigned char *) 0x001FA400;
	volatile  unsigned char *src0=Ptr+1;
    volatile  unsigned char *src1=Ptr;
    volatile  unsigned char *src2=Ptr+2;
    volatile  unsigned char *dst0=Y;
    volatile  unsigned char *dst1=Cb;
    volatile  unsigned char *dst2=Cr;
        ////////////////////////////////////////////////////////////
    
    // configure MemDMA0 Source0 Descriptor block in memory
    us_MemDMA0_Src0_Descriptor1[0] = (unsigned short)((unsigned int)us_MemDMA0_Src1_Descriptor1 & 0xffff);
	us_MemDMA0_Src0_Descriptor1[1] = (unsigned short)((unsigned int)us_MemDMA0_Src1_Descriptor1 >> 16);
	us_MemDMA0_Src0_Descriptor1[2] = (unsigned short)((unsigned int)src0 & 0xffff);
	us_MemDMA0_Src0_Descriptor1[3] = (unsigned short)((unsigned int)src0 >> 16);
	us_MemDMA0_Src0_Descriptor1[4] = 0x7931;
	us_MemDMA0_Src0_Descriptor1[5] = 352;
	us_MemDMA0_Src0_Descriptor1[6] = 4;
	us_MemDMA0_Src0_Descriptor1[7] = 288;
	us_MemDMA0_Src0_Descriptor1[8] = 36;
	///////////////////////////////////////////////////////////////
	
	// configure MemDMA0 Source1 Descriptor block in memory
    us_MemDMA0_Src1_Descriptor1[0] = (unsigned short)((unsigned int)us_MemDMA0_Src2_Descriptor1 & 0xffff);
	us_MemDMA0_Src1_Descriptor1[1] = (unsigned short)((unsigned int)us_MemDMA0_Src2_Descriptor1 >> 16);
	us_MemDMA0_Src1_Descriptor1[2] = (unsigned short)((unsigned int)src1 & 0xffff);
	us_MemDMA0_Src1_Descriptor1[3] = (unsigned short)((unsigned int)src1 >> 16);
	us_MemDMA0_Src1_Descriptor1[4] = 0x7931;
	us_MemDMA0_Src1_Descriptor1[5] = 176;
	us_MemDMA0_Src1_Descriptor1[6] = 8;
    us_MemDMA0_Src1_Descriptor1[7] = 144;
	us_MemDMA0_Src1_Descriptor1[8] = 1480;
	////////////////////////////////////////////////////////////
	// configure MemDMA0 Source2 Descriptor block in memory
    us_MemDMA0_Src2_Descriptor1[0] = (unsigned short)((unsigned int)us_MemDMA0_END1 & 0xffff);
	us_MemDMA0_Src2_Descriptor1[1] = (unsigned short)((unsigned int)us_MemDMA0_END1 >> 16);
	us_MemDMA0_Src2_Descriptor1[2] = (unsigned short)((unsigned int)src2 & 0xffff);
	us_MemDMA0_Src2_Descriptor1[3] = (unsigned short)((unsigned int)src2 >> 16);
	us_MemDMA0_Src2_Descriptor1[4] = 0x79b1;
	us_MemDMA0_Src2_Descriptor1[5] = 176;
	us_MemDMA0_Src2_Descriptor1[6] = 8;
	us_MemDMA0_Src2_Descriptor1[7] = 144;
	us_MemDMA0_Src2_Descriptor1[8] = 1480;
	///////////////////////////////////////////////////////////////////
	

	// configure MemDMA0 Destination Descriptor block in memory
	us_MemDMA0_Dst0_Descriptor1[0] = (unsigned short)((unsigned int)us_MemDMA0_Dst1_Descriptor1 & 0xffff);
	us_MemDMA0_Dst0_Descriptor1[1] = (unsigned short)((unsigned int)us_MemDMA0_Dst1_Descriptor1 >> 16);
	us_MemDMA0_Dst0_Descriptor1[2] = (unsigned short)((unsigned int)dst0 & 0xffff);
	us_MemDMA0_Dst0_Descriptor1[3] = (unsigned short)((unsigned int)dst0 >> 16);
	us_MemDMA0_Dst0_Descriptor1[4] = 0x7933;
	us_MemDMA0_Dst0_Descriptor1[5] = 352;
	us_MemDMA0_Dst0_Descriptor1[6] = 1;
	us_MemDMA0_Dst0_Descriptor1[7] = 288;
	us_MemDMA0_Dst0_Descriptor1[8] = 1;
	///////////////////////////////////////////////////////////
	
	// configure MemDMA0 Destination Descriptor block in memory
	us_MemDMA0_Dst1_Descriptor1[0] = (unsigned short)((unsigned int)us_MemDMA0_Dst2_Descriptor1 & 0xffff);
	us_MemDMA0_Dst1_Descriptor1[1] = (unsigned short)((unsigned int)us_MemDMA0_Dst2_Descriptor1 >> 16);
	us_MemDMA0_Dst1_Descriptor1[2] = (unsigned short)((unsigned int)dst1 & 0xffff);
	us_MemDMA0_Dst1_Descriptor1[3] = (unsigned short)((unsigned int)dst1 >> 16);
	us_MemDMA0_Dst1_Descriptor1[4] = 0x7933;
	us_MemDMA0_Dst1_Descriptor1[5] = 176;
	us_MemDMA0_Dst1_Descriptor1[6] = 1;
	us_MemDMA0_Dst1_Descriptor1[7] = 144;
	us_MemDMA0_Dst1_Descriptor1[8] = 1;
	////////////////////////////////////////////////////////////////
	
	// configure MemDMA0 Destination Descriptor block in memory
	us_MemDMA0_Dst2_Descriptor1[0] = (unsigned short)((unsigned int)us_MemDMA0_END1 & 0xffff);
	us_MemDMA0_Dst2_Descriptor1[1] = (unsigned short)((unsigned int)us_MemDMA0_END1 >> 16);
	us_MemDMA0_Dst2_Descriptor1[2] = (unsigned short)((unsigned int)dst2 & 0xffff);
	us_MemDMA0_Dst2_Descriptor1[3] = (unsigned short)((unsigned int)dst2 >> 16);
	us_MemDMA0_Dst2_Descriptor1[4] = 0x79b3;
	us_MemDMA0_Dst2_Descriptor1[5] = 176;
	us_MemDMA0_Dst2_Descriptor1[6] = 1;
	us_MemDMA0_Dst2_Descriptor1[7] = 144;
	us_MemDMA0_Dst2_Descriptor1[8] = 1;
	///////////////////////////////////////////////////////////
		
	us_MemDMA0_END1[0]  = (unsigned short)((unsigned int)us_MemDMA0_END1 & 0xffff);
	us_MemDMA0_END1[1]  = (unsigned short)((unsigned int)us_MemDMA0_END1 >> 16);
	us_MemDMA0_END1[2]  = (unsigned short)((unsigned int)us_MemDMA0_END1 & 0xffff);
	us_MemDMA0_END1[3]  = (unsigned short)((unsigned int)us_MemDMA0_END1 >> 16);
	us_MemDMA0_END1[4]  = 0;
//    unsigned short Done=*pDMA0_IRQ_STATUS;
//    Done=Done&0x0001;
//    while(!done);
	// enable MemDMA0 transfers
	*pMDMA_S0_NEXT_DESC_PTR	= us_MemDMA0_Src0_Descriptor1;
	*pMDMA_D0_NEXT_DESC_PTR	= us_MemDMA0_Dst0_Descriptor1;
	*pMDMA_S0_CONFIG		= 0x7931;
	*pMDMA_D0_CONFIG		= 0x7933;
	//Target address of the DMA
/*	*pMDMA_S0_START_ADDR = 0x01;	

	//Line_Length 16bit transfers will be executed
	*pMDMA_S0_X_COUNT = 352;

	//The modifier is set to 2 because of the 16bit transfers
	*pMDMA_S0_X_MODIFY = 4;	
														
	//Frame_Length 16bit transfers will be executed
	*pMDMA_S0_Y_COUNT = 288;

	//The modifier is set to 2 because of the 16bit transfers
	*pMDMA_S0_Y_MODIFY = 36;	
	
	
    /////////////////////////////
    *pMDMA_D0_START_ADDR = 0x0012FC00;	

	//Line_Length 16bit transfers will be executed
	*pMDMA_D0_X_COUNT = 352;

	//The modifier is set to 2 because of the 16bit transfers
	*pMDMA_D0_X_MODIFY = 1;	
														
	//Frame_Length 16bit transfers will be executed
	*pMDMA_D0_Y_COUNT = 288;

	//The modifier is set to 2 because of the 16bit transfers
	*pMDMA_D0_Y_MODIFY = 1;	
	//DMA Config: Enable DMA | Memory write DMA | 2-D DMA | Discard DMA FIFO before start | enable assertation of interrupt | NDSIZE for stop mode | Enable STOP DMA
	*pMDMA_S0_CONFIG = DMAEN | DI_EN |WDSIZE_8| DMA2D | RESTART | DI_EN;	
	//DMA Config: Enable DMA | Memory write DMA | 2-D DMA | Discard DMA FIFO before start | enable assertation of interrupt | NDSIZE for stop mode | Enable STOP DMA
	*pMDMA_D0_CONFIG = DMAEN | DI_EN | WNR | WDSIZE_8| DMA2D | RESTART | DI_EN;	
	
*/	
}