performance.map.summary

来自「用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Sun May 21 21:11:49 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : performance
Top-level Entity Name : performance
Family : Stratix
Total logic elements : 16
Total pins : 12
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0