multiplex.map.rpt

复接程序,用quartus运行的,可以把很多个信号复接在一起,是程序的一部分!

; Maximum Number of M-RAM Memory Blocks                              ; -1                 ; -1                 ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                        ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                    ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------+
; multiplex.v                      ; yes             ; User Verilog HDL File  ; C:/Documents and Settings/new/桌面/已调试/multiplex/multiplex.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Total logic elements                        ; 7        ;
;     -- Combinational with no register       ; 3        ;
;     -- Register only                        ; 0        ;
;     -- Combinational with a register        ; 4        ;
;                                             ;          ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 6        ;
;     -- 3 input functions                    ; 1        ;
;     -- 2 input functions                    ; 0        ;
;     -- 1 input functions                    ; 0        ;
;     -- 0 input functions                    ; 0        ;
;         -- Combinational cells for routing  ; 0        ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 7        ;
;     -- arithmetic mode                      ; 0        ;
;     -- qfbk mode                            ; 0        ;
;     -- register cascade mode                ; 0        ;
;     -- synchronous clear/load mode          ; 0        ;
;     -- asynchronous clear/load mode         ; 4        ;
;                                             ;          ;
; Total registers                             ; 4        ;
; I/O pins                                    ; 6        ;
; Maximum fan-out node                        ; count[2] ;
; Maximum fan-out                             ; 6        ;
; Total fan-out                               ; 36       ;
; Average fan-out                             ; 2.77     ;
+---------------------------------------------+----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |multiplex                 ; 7 (7)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 6    ; 0            ; 3 (3)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |multiplex          ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/new/桌面/已调试/multiplex/multiplex.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Aug 22 07:46:39 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off multiplex -c multiplex
Info: Found 1 design units, including 1 entities, in source file multiplex.v
    Info: Found entity 1: multiplex
Info: Elaborating entity "multiplex" for the top level hierarchy
Warning (10235): Verilog HDL Always Construct warning at multiplex.v(39): variable "count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at multiplex.v(43): variable "count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at multiplex.v(47): variable "count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info: Implemented 13 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 1 output pins
    Info: Implemented 7 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Tue Aug 22 07:46:41 2006
    Info: Elapsed time: 00:00:02