multiplex.tan.rpt

复接程序,用quartus运行的,可以把很多个信号复接在一起,是程序的一部分!

; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[0] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 0.907 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[0] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 0.905 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[0] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 0.903 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[1] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 0.752 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[1] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 0.752 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[1] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 0.751 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[2] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 0.703 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[2] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 0.702 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[2] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 0.701 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[2] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 0.699 ns                ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+----------+----+------------+
; Slack ; Required tco ; Actual tco ; From     ; To ; From Clock ;
+-------+--------------+------------+----------+----+------------+
; N/A   ; None         ; 7.664 ns   ; count[2] ; X  ; clk        ;
; N/A   ; None         ; 7.535 ns   ; count[1] ; X  ; clk        ;
; N/A   ; None         ; 7.439 ns   ; count[0] ; X  ; clk        ;
; N/A   ; None         ; 6.711 ns   ; count[3] ; X  ; clk        ;
+-------+--------------+------------+----------+----+------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 8.982 ns        ; Xs   ; X  ;
; N/A   ; None              ; 8.712 ns        ; X1p  ; X  ;
; N/A   ; None              ; 8.417 ns        ; X2p  ; X  ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Aug 22 07:47:01 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off multiplex -c multiplex --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "count[3]" and destination register "count[0]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.986 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y1_N8; Fanout = 5; REG Node = 'count[3]'
            Info: 2: + IC(0.447 ns) + CELL(0.539 ns) = 0.986 ns; Loc. = LC_X52_Y1_N6; Fanout = 5; REG Node = 'count[0]'
            Info: Total cell delay = 0.539 ns ( 54.67 % )
            Info: Total interconnect delay = 0.447 ns ( 45.33 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.917 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.650 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X52_Y1_N6; Fanout = 5; REG Node = 'count[0]'
                Info: Total cell delay = 1.267 ns ( 43.44 % )
                Info: Total interconnect delay = 1.650 ns ( 56.56 % )
            Info: - Longest clock path from clock "clk" to source register is 2.917 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.650 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X52_Y1_N8; Fanout = 5; REG Node = 'count[3]'
                Info: Total cell delay = 1.267 ns ( 43.44 % )
                Info: Total interconnect delay = 1.650 ns ( 56.56 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock "clk" to destination pin "X" through register "count[2]" is 7.664 ns
    Info: + Longest clock path from clock "clk" to source register is 2.917 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.650 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X52_Y1_N9; Fanout = 6; REG Node = 'count[2]'
        Info: Total cell delay = 1.267 ns ( 43.44 % )
        Info: Total interconnect delay = 1.650 ns ( 56.56 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.591 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y1_N9; Fanout = 6; REG Node = 'count[2]'
        Info: 2: + IC(0.466 ns) + CELL(0.280 ns) = 0.746 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; COMB Node = 'X~315'
        Info: 3: + IC(0.350 ns) + CELL(0.366 ns) = 1.462 ns; Loc. = LC_X52_Y1_N4; Fanout = 1; COMB Node = 'X~317'
        Info: 4: + IC(0.753 ns) + CELL(2.376 ns) = 4.591 ns; Loc. = PIN_V4; Fanout = 0; PIN Node = 'X'
        Info: Total cell delay = 3.022 ns ( 65.82 % )
        Info: Total interconnect delay = 1.569 ns ( 34.18 % )
Info: Longest tpd from source pin "Xs" to destination pin "X" is 8.982 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W3; Fanout = 1; PIN Node = 'Xs'
    Info: 2: + IC(3.684 ns) + CELL(0.366 ns) = 5.137 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; COMB Node = 'X~315'
    Info: 3: + IC(0.350 ns) + CELL(0.366 ns) = 5.853 ns; Loc. = LC_X52_Y1_N4; Fanout = 1; COMB Node = 'X~317'
    Info: 4: + IC(0.753 ns) + CELL(2.376 ns) = 8.982 ns; Loc. = PIN_V4; Fanout = 0; PIN Node = 'X'
    Info: Total cell delay = 4.195 ns ( 46.70 % )
    Info: Total interconnect delay = 4.787 ns ( 53.30 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Aug 22 07:47:02 2006
    Info: Elapsed time: 00:00:01