📄 permute.v
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module permute(interleaver,clk,InfoSeq,scramble);
input [3:0]interleaver;
input clk;
input InfoSeq;
output scramble;
reg scramble;
reg buffer[14:0];
integer j=0,count=0;
always@(posedge clk)
begin
buffer[interleaver]=InfoSeq;
count=count+1;
end
always@(posedge clk)
begin
if(count>14)
begin
if(j<15)
begin
scramble=buffer[j];
j=j+1;
end
else scramble=0;
end
end
endmodule
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