randn.v

来自「随机序列发生器,是一个m序列,生成函数都写在里面,位宽为4,可以改变!」· Verilog 代码 · 共 39 行

module randn(clk,
             Cin,
             Dout,
             out);

parameter Width=4;

input clk;
input [Width-1:0] Cin;
output [Width-1:0] Dout;
output out;

reg [Width-1:0] Dout;
wire [Width-1:0] Buff;
wire shift;

function Count;
  input [Width-1:0] A;
  integer K;
  begin
     Count=0;
     for(K=0;K<Width;K=K+1)
        if(A[K])Count=Count+1;
  end
endfunction

always@(posedge clk)
  begin
    if(Dout==0)Dout<=1;
    else
       Dout<={shift,Dout[Width-1:1]};
  end

assign Buff=Dout & Cin;
assign shift=Count(Buff)%2;
//assign shift=Buff[3]^Buff[2]^Buff[1]^Buff[0];
assign out=Dout[0];

endmodule