randn.fit.qmsg

随机序列发生器,是一个m序列,生成函数都写在里面,位宽为4,可以改变!

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "9 unused 3.30 4 5 0 " "Info: Number of I/O pins in group: 9 (unused VREF, 3.30 VCCIO, 4 input, 5 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 11 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 17 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.272 ns register register " "Info: Estimated most critical path is register to register delay of 1.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Dout\[0\]~reg0 1 REG LAB_X6_Y13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y13; Fanout = 4; REG Node = 'Dout\[0\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "" { Dout[0]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.157 ns) + CELL(0.454 ns) 0.611 ns Dout~92 2 COMB LAB_X6_Y13 1 " "Info: 2: + IC(0.157 ns) + CELL(0.454 ns) = 0.611 ns; Loc. = LAB_X6_Y13; Fanout = 1; COMB Node = 'Dout~92'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "0.611 ns" { Dout[0]~reg0 Dout~92 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.238 ns) 1.272 ns Dout\[3\]~reg0 3 REG LAB_X6_Y13 4 " "Info: 3: + IC(0.423 ns) + CELL(0.238 ns) = 1.272 ns; Loc. = LAB_X6_Y13; Fanout = 4; REG Node = 'Dout\[3\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "0.661 ns" { Dout~92 Dout[3]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.692 ns 54.40 % " "Info: Total cell delay = 0.692 ns ( 54.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.580 ns 45.60 % " "Info: Total interconnect delay = 0.580 ns ( 45.60 % )" {  } {  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "1.272 ns" { Dout[0]~reg0 Dout~92 Dout[3]~reg0 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 19 10:33:46 2006 " "Info: Processing ended: Wed Jul 19 10:33:46 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}