randn.map.qmsg

随机序列发生器,是一个m序列,生成函数都写在里面,位宽为4,可以改变!

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 19 10:33:36 2006 " "Info: Processing started: Wed Jul 19 10:33:36 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off randn -c randn " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off randn -c randn" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "randn.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file randn.v" { { "Info" "ISGN_ENTITY_NAME" "1 randn " "Info: Found entity 1: randn" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "randn " "Info: Elaborating entity \"randn\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 randn.v(29) " "Warning: Verilog HDL assignment warning at randn.v(29): truncated value with size 32 to match size of target (4)" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 29 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 randn.v(21) " "Warning: Verilog HDL assignment warning at randn.v(21): truncated value with size 32 to match size of target (1)" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 randn.v(23) " "Warning: Verilog HDL assignment warning at randn.v(23): truncated value with size 32 to match size of target (1)" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 randn.v(35) " "Warning: Verilog HDL assignment warning at randn.v(35): truncated value with size 32 to match size of target (1)" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 35 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "16 " "Info: Implemented 16 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "6 " "Info: Implemented 6 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 19 10:33:39 2006 " "Info: Processing ended: Wed Jul 19 10:33:39 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}