randn.tan.qmsg

随机序列发生器,是一个m序列,生成函数都写在里面,位宽为4,可以改变!

{ "Info" "ITDB_TSU_RESULT" "Dout\[3\]~reg0 Cin\[2\] clk 4.605 ns register " "Info: tsu for register \"Dout\[3\]~reg0\" (data pin = \"Cin\[2\]\", clock pin = \"clk\") is 4.605 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.704 ns + Longest pin register " "Info: + Longest pin to register delay is 6.704 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Cin\[2\] 1 PIN PIN_98 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_98; Fanout = 1; PIN Node = 'Cin\[2\]'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "" { Cin[2] } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.833 ns) + CELL(0.340 ns) 5.308 ns Dout~92 2 COMB LC_X6_Y13_N2 1 " "Info: 2: + IC(3.833 ns) + CELL(0.340 ns) = 5.308 ns; Loc. = LC_X6_Y13_N2; Fanout = 1; COMB Node = 'Dout~92'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "4.173 ns" { Cin[2] Dout~92 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.828 ns) + CELL(0.568 ns) 6.704 ns Dout\[3\]~reg0 3 REG LC_X6_Y13_N6 4 " "Info: 3: + IC(0.828 ns) + CELL(0.568 ns) = 6.704 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout\[3\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "1.396 ns" { Dout~92 Dout[3]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.043 ns 30.47 % " "Info: Total cell delay = 2.043 ns ( 30.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.661 ns 69.53 % " "Info: Total interconnect delay = 4.661 ns ( 69.53 % )" {  } {  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "6.704 ns" { Cin[2] Dout~92 Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.704 ns" { Cin[2] Cin[2]~out0 Dout~92 Dout[3]~reg0 } { 0.000ns 0.000ns 3.833ns 0.828ns } { 0.000ns 1.135ns 0.340ns 0.568ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.128 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "" { clk } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns Dout\[3\]~reg0 2 REG LC_X6_Y13_N6 4 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout\[3\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "0.998 ns" { clk Dout[3]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[3]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "6.704 ns" { Cin[2] Dout~92 Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.704 ns" { Cin[2] Cin[2]~out0 Dout~92 Dout[3]~reg0 } { 0.000ns 0.000ns 3.833ns 0.828ns } { 0.000ns 1.135ns 0.340ns 0.568ns } } } { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[3]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out Dout\[0\]~reg0 5.893 ns register " "Info: tco from clock \"clk\" to destination pin \"out\" through register \"Dout\[0\]~reg0\" is 5.893 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.128 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "" { clk } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns Dout\[0\]~reg0 2 REG LC_X6_Y13_N8 4 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X6_Y13_N8; Fanout = 4; REG Node = 'Dout\[0\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "0.998 ns" { clk Dout[0]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[0]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.592 ns + Longest register pin " "Info: + Longest register to pin delay is 3.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Dout\[0\]~reg0 1 REG LC_X6_Y13_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y13_N8; Fanout = 4; REG Node = 'Dout\[0\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "" { Dout[0]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.970 ns) + CELL(1.622 ns) 3.592 ns out 2 PIN PIN_28 0 " "Info: 2: + IC(1.970 ns) + CELL(1.622 ns) = 3.592 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'out'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "3.592 ns" { Dout[0]~reg0 out } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 45.16 % " "Info: Total cell delay = 1.622 ns ( 45.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.970 ns 54.84 % " "Info: Total interconnect delay = 1.970 ns ( 54.84 % )" {  } {  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "3.592 ns" { Dout[0]~reg0 out } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.592 ns" { Dout[0]~reg0 out } { 0.000ns 1.970ns } { 0.000ns 1.622ns } } }  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[0]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "3.592 ns" { Dout[0]~reg0 out } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.592 ns" { Dout[0]~reg0 out } { 0.000ns 1.970ns } { 0.000ns 1.622ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "Dout\[3\]~reg0 Cin\[1\] clk -3.251 ns register " "Info: th for register \"Dout\[3\]~reg0\" (data pin = \"Cin\[1\]\", clock pin = \"clk\") is -3.251 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.128 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "" { clk } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns Dout\[3\]~reg0 2 REG LC_X6_Y13_N6 4 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout\[3\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "0.998 ns" { clk Dout[3]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[3]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.391 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.391 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Cin\[1\] 1 PIN PIN_92 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_92; Fanout = 1; PIN Node = 'Cin\[1\]'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "" { Cin[1] } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.888 ns) + CELL(0.368 ns) 5.391 ns Dout\[3\]~reg0 2 REG LC_X6_Y13_N6 4 " "Info: 2: + IC(3.888 ns) + CELL(0.368 ns) = 5.391 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout\[3\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "4.256 ns" { Cin[1] Dout[3]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.503 ns 27.88 % " "Info: Total cell delay = 1.503 ns ( 27.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.888 ns 72.12 % " "Info: Total interconnect delay = 3.888 ns ( 72.12 % )" {  } {  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "5.391 ns" { Cin[1] Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "5.391 ns" { Cin[1] Cin[1]~out0 Dout[3]~reg0 } { 0.000ns 0.000ns 3.888ns } { 0.000ns 1.135ns 0.368ns } } }  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[3]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "5.391 ns" { Cin[1] Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "5.391 ns" { Cin[1] Cin[1]~out0 Dout[3]~reg0 } { 0.000ns 0.000ns 3.888ns } { 0.000ns 1.135ns 0.368ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 19 10:33:54 2006 " "Info: Processing ended: Wed Jul 19 10:33:54 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}