randn.tan.qmsg

随机序列发生器,是一个m序列,生成函数都写在里面,位宽为4,可以改变!

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 19 10:33:53 2006 " "Info: Processing started: Wed Jul 19 10:33:53 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off randn -c randn --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off randn -c randn --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 8 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register Dout\[0\]~reg0 register Dout\[3\]~reg0 340.83 MHz 2.934 ns Internal " "Info: Clock \"clk\" has Internal fmax of 340.83 MHz between source register \"Dout\[0\]~reg0\" and destination register \"Dout\[3\]~reg0\" (period= 2.934 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.732 ns + Longest register register " "Info: + Longest register to register delay is 2.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Dout\[0\]~reg0 1 REG LC_X6_Y13_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y13_N8; Fanout = 4; REG Node = 'Dout\[0\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "" { Dout[0]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.882 ns) + CELL(0.454 ns) 1.336 ns Dout~92 2 COMB LC_X6_Y13_N2 1 " "Info: 2: + IC(0.882 ns) + CELL(0.454 ns) = 1.336 ns; Loc. = LC_X6_Y13_N2; Fanout = 1; COMB Node = 'Dout~92'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "1.336 ns" { Dout[0]~reg0 Dout~92 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.828 ns) + CELL(0.568 ns) 2.732 ns Dout\[3\]~reg0 3 REG LC_X6_Y13_N6 4 " "Info: 3: + IC(0.828 ns) + CELL(0.568 ns) = 2.732 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout\[3\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "1.396 ns" { Dout~92 Dout[3]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.022 ns 37.41 % " "Info: Total cell delay = 1.022 ns ( 37.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.710 ns 62.59 % " "Info: Total interconnect delay = 1.710 ns ( 62.59 % )" {  } {  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.732 ns" { Dout[0]~reg0 Dout~92 Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.732 ns" { Dout[0]~reg0 Dout~92 Dout[3]~reg0 } { 0.000ns 0.882ns 0.828ns } { 0.000ns 0.454ns 0.568ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.128 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "" { clk } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns Dout\[3\]~reg0 2 REG LC_X6_Y13_N6 4 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout\[3\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "0.998 ns" { clk Dout[3]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[3]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.128 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "" { clk } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns Dout\[0\]~reg0 2 REG LC_X6_Y13_N8 4 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X6_Y13_N8; Fanout = 4; REG Node = 'Dout\[0\]~reg0'" {  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "0.998 ns" { clk Dout[0]~reg0 } "NODE_NAME" } "" } } { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[0]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[3]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[0]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "randn.v" "" { Text "E:/altera/quartus50/randn/randn.v" 32 -1 0 } }  } 0}  } { { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.732 ns" { Dout[0]~reg0 Dout~92 Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.732 ns" { Dout[0]~reg0 Dout~92 Dout[3]~reg0 } { 0.000ns 0.882ns 0.828ns } { 0.000ns 0.454ns 0.568ns } } } { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[3]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "E:/altera/quartus50/randn/db/randn_cmp.qrpt" "" { Report "E:/altera/quartus50/randn/db/randn_cmp.qrpt" Compiler "randn" "UNKNOWN" "V1" "E:/altera/quartus50/randn/db/randn.quartus_db" { Floorplan "E:/altera/quartus50/randn/" "" "2.128 ns" { clk Dout[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 Dout[0]~reg0 } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}