randn.tan.rpt

随机序列发生器,是一个m序列,生成函数都写在里面,位宽为4,可以改变!

; Slack ; Required tsu ; Actual tsu ; From   ; To           ; To Clock ;
+-------+--------------+------------+--------+--------------+----------+
; N/A   ; None         ; 4.605 ns   ; Cin[2] ; Dout[3]~reg0 ; clk      ;
; N/A   ; None         ; 4.563 ns   ; Cin[0] ; Dout[3]~reg0 ; clk      ;
; N/A   ; None         ; 4.239 ns   ; Cin[3] ; Dout[3]~reg0 ; clk      ;
; N/A   ; None         ; 3.292 ns   ; Cin[1] ; Dout[3]~reg0 ; clk      ;
+-------+--------------+------------+--------+--------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 5.893 ns   ; Dout[0]~reg0 ; out     ; clk        ;
; N/A   ; None         ; 5.893 ns   ; Dout[0]~reg0 ; Dout[0] ; clk        ;
; N/A   ; None         ; 5.165 ns   ; Dout[2]~reg0 ; Dout[2] ; clk        ;
; N/A   ; None         ; 4.921 ns   ; Dout[3]~reg0 ; Dout[3] ; clk        ;
; N/A   ; None         ; 4.915 ns   ; Dout[1]~reg0 ; Dout[1] ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+--------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To           ; To Clock ;
+---------------+-------------+-----------+--------+--------------+----------+
; N/A           ; None        ; -3.251 ns ; Cin[1] ; Dout[3]~reg0 ; clk      ;
; N/A           ; None        ; -4.198 ns ; Cin[3] ; Dout[3]~reg0 ; clk      ;
; N/A           ; None        ; -4.522 ns ; Cin[0] ; Dout[3]~reg0 ; clk      ;
; N/A           ; None        ; -4.564 ns ; Cin[2] ; Dout[3]~reg0 ; clk      ;
+---------------+-------------+-----------+--------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Jul 19 10:33:53 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off randn -c randn --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 340.83 MHz between source register "Dout[0]~reg0" and destination register "Dout[3]~reg0" (period= 2.934 ns)
    Info: + Longest register to register delay is 2.732 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y13_N8; Fanout = 4; REG Node = 'Dout[0]~reg0'
        Info: 2: + IC(0.882 ns) + CELL(0.454 ns) = 1.336 ns; Loc. = LC_X6_Y13_N2; Fanout = 1; COMB Node = 'Dout~92'
        Info: 3: + IC(0.828 ns) + CELL(0.568 ns) = 2.732 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout[3]~reg0'
        Info: Total cell delay = 1.022 ns ( 37.41 % )
        Info: Total interconnect delay = 1.710 ns ( 62.59 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.128 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout[3]~reg0'
            Info: Total cell delay = 1.677 ns ( 78.81 % )
            Info: Total interconnect delay = 0.451 ns ( 21.19 % )
        Info: - Longest clock path from clock "clk" to source register is 2.128 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X6_Y13_N8; Fanout = 4; REG Node = 'Dout[0]~reg0'
            Info: Total cell delay = 1.677 ns ( 78.81 % )
            Info: Total interconnect delay = 0.451 ns ( 21.19 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "Dout[3]~reg0" (data pin = "Cin[2]", clock pin = "clk") is 4.605 ns
    Info: + Longest pin to register delay is 6.704 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_98; Fanout = 1; PIN Node = 'Cin[2]'
        Info: 2: + IC(3.833 ns) + CELL(0.340 ns) = 5.308 ns; Loc. = LC_X6_Y13_N2; Fanout = 1; COMB Node = 'Dout~92'
        Info: 3: + IC(0.828 ns) + CELL(0.568 ns) = 6.704 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout[3]~reg0'
        Info: Total cell delay = 2.043 ns ( 30.47 % )
        Info: Total interconnect delay = 4.661 ns ( 69.53 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.128 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout[3]~reg0'
        Info: Total cell delay = 1.677 ns ( 78.81 % )
        Info: Total interconnect delay = 0.451 ns ( 21.19 % )
Info: tco from clock "clk" to destination pin "out" through register "Dout[0]~reg0" is 5.893 ns
    Info: + Longest clock path from clock "clk" to source register is 2.128 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X6_Y13_N8; Fanout = 4; REG Node = 'Dout[0]~reg0'
        Info: Total cell delay = 1.677 ns ( 78.81 % )
        Info: Total interconnect delay = 0.451 ns ( 21.19 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.592 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y13_N8; Fanout = 4; REG Node = 'Dout[0]~reg0'
        Info: 2: + IC(1.970 ns) + CELL(1.622 ns) = 3.592 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'out'
        Info: Total cell delay = 1.622 ns ( 45.16 % )
        Info: Total interconnect delay = 1.970 ns ( 54.84 % )
Info: th for register "Dout[3]~reg0" (data pin = "Cin[1]", clock pin = "clk") is -3.251 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.128 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout[3]~reg0'
        Info: Total cell delay = 1.677 ns ( 78.81 % )
        Info: Total interconnect delay = 0.451 ns ( 21.19 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 5.391 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_92; Fanout = 1; PIN Node = 'Cin[1]'
        Info: 2: + IC(3.888 ns) + CELL(0.368 ns) = 5.391 ns; Loc. = LC_X6_Y13_N6; Fanout = 4; REG Node = 'Dout[3]~reg0'
        Info: Total cell delay = 1.503 ns ( 27.88 % )
        Info: Total interconnect delay = 3.888 ns ( 72.12 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jul 19 10:33:54 2006
    Info: Elapsed time: 00:00:02