smbus_master_f31x.c

c8051f的IIC读取eeprom,有很好的程序结构

//------------------------------------------------------------------------------------
// SMBus_Init()
//------------------------------------------------------------------------------------
//
// SMBus configured as follows:
// - SMBus enabled
// - Slave mode disabled
// - Timer1 used as clock source. The maximum SCL frequency will be approximately
//   1/3 the Timer1 overflow rate
// - Setup and hold time extensions enabled
// - Free and SCL low timeout detection enabled
//
void SMBus_Init (void)
{
   SMB0CF = 0x5D;                            // Use Timer1 overflows as SMBus clock 
                                             // source
                                             // Disable slave mode
                                             // Enable setup & hold time extensions
                                             // Enable SMBus Free timeout detect
                                             // Enable SCL low timeout detect

   SMB0CF |= 0x80;                           // Enable SMBus;
}

//------------------------------------------------------------------------------------
// Timer3_Init()
//------------------------------------------------------------------------------------
//
// Timer3 configured for use by the SMBus low timeout detect feature as follows:
// - Timer3 in 16-bit auto-reload mode
// - SYSCLK/12 as Timer3 clock source
// - Timer3 reload registers loaded for a 25ms overflow period
// - Timer3 pre-loaded to overflow after 25ms
// - Timer3 enabled
//
void Timer3_Init (void)
{
   TMR3CN = 0x00;                            // Timer3 configured for 16-bit
                                             // auto-reload, low-byte
                                             // interrupt disabled

   TMR3 = -(SYSCLK/12/40);                   // Timer3 configured to overflow after
   TMR3RL = -(SYSCLK/12/40);                 // ~25ms (for SMBus low timeout detect)


   CKCON &= ~0x40;                           // Timer3 uses SYSCLK/12
   TMR3 |= 0x04;                             // Start Timer3
}

//------------------------------------------------------------------------------------
// Timer1_Init()
//------------------------------------------------------------------------------------
//
// Timer1 configured as the SMBus clock source as follows:
// - Timer1 in 8-bit auto-reload mode
// - SYSCLK / 12 as Timer1 clock source
// - Timer1 overflow rate => 3 * SMB_FREQUENCY
// - The resulting SCL clock rate will be ~1/3 the Timer1 overflow rate
// - Timer1 enabled
//
void Timer1_Init (void)
{
   CKCON &= ~0x0B;                           // Timer1 clock source = SYSCLK / 12
   TMOD = 0x20;                              // Timer1 in 8-bit auto-reload mode

   TH1 = -(SYSCLK/SMB_FREQUENCY/12/3);       // Timer1 configured to overflow at 1/3
                                             // the rate defined by SMB_FREQUENCY

   TL1 = -(SYSCLK/SMB_FREQUENCY/12/3);       // Timer1 preloaded to overflow at 1/3
                                             // the rate defined by SMB_FREQUENCY

   TR1 = 1;                                  // Timer1 enabled
}

//-----------------------------------------------------------------------------------
// PORT_Init
//-----------------------------------------------------------------------------------
//
// Configure the Crossbar and GPIO ports.
// P0.0 - SDA
// P0.1 - SCL
// P0.2 -
// P0.3 -
// P0.4 -
// P0.5 -
// P0.6 -
// P0.7 -
//
void Port_Init (void)
{
   XBR0 = 0x04;                              // Enable SMBus pins
   XBR1 = 0x40;                              // Enable crossbar and weak pull-ups

   P0MDIN = 0xFF;                            // All P0 pins digital input

   P0MDOUT = 0x00;                           // All P0 pins open-drain output
   P0 = 0xFF;                                //

   P3MDOUT |= 0x08;                          // P3.3 push-pull output
}

//------------------------------------------------------------------------------------
// SMBus Interrupt Service Routine (ISR)
//------------------------------------------------------------------------------------
//
// SMBus ISR state machine
// - Master only implementation - no slave or arbitration states defined
// - All incoming data is written to global variable <SMB_DATA_IN>
// - All outgoing data is read from global variable <SMB_DATA_OUT>
//
void SMBus_ISR (void) interrupt 7
{
   bit FAIL;                                 // Used by the ISR to flag failed
                                             // transfers
   static bit ADDR_SEND;                     // Used by the ISR to flag byte
                                             // transmissions as slave addresses

   switch (SMB0CN & 0xF0)                    // Status vector
   {
      // Master Transmitter/Receiver: START condition transmitted.
      case SMB_MTSTA:
         SMB0DAT = TARGET;                   // Load address of the target slave
         SMB0DAT |= SMB_RW;                  // Load R/W bit
         STA = 0;                            // Manually clear START bit
         ADDR_SEND = 1;
         break;

      // Master Transmitter: Data byte transmitted
      case SMB_MTDB:
         if (ACK)                            // Slave ACK?
         {
            if (ADDR_SEND)                   // If the previous byte was a slave
            {                                // address,
               ADDR_SEND = 0;                // Next byte is not a slave address
               if (SMB_RW==WRITE)            // If this transfer is a WRITE,
               {
                  SMB0DAT = SMB_DATA_OUT;    // send data byte
               }
               else {}                       // If this transfer is a READ,
                                             // proceed with transfer without
                                             // writing to SMB0DAT (switch
                                             // to receive mode)
            }
            else                             // If previous byte was not a slave
            {                                // address,
               STO = 1;                      // set STO to terminte transfer
               SMB_BUSY = 0;                 // and free SMBus interface
            }
         }
         else                                // If slave NACK,
         {
            FAIL = 1;                        // Indicate failed transfer
                                             // and handle at end of ISR
         }
         break;

      // Master Receiver: byte received
      case SMB_MRDB:
         SMB_DATA_IN = SMB0DAT;              // Store received byte
         SMB_BUSY = 0;                       // Free SMBus interface
         ACK = 0;                            // Send NACK to indicate last byte
                                             // of this transfer

         STO = 1;                            // Send STOP to terminate transfer
         break;

      default:
         FAIL = 1;                           // Indicate failed transfer
                                             // and handle at end of ISR
         break;
   
   } // end switch

   if (FAIL)                                 // If the transfer failed,
   {
      SMB0CN &= ~0x40;                       // Reset communication
      SMB0CN |= 0x40;
      SMB_BUSY = 0;                          // Free SMBus
   }

   SI=0;                                     // clear interrupt flag
}

//-----------------------------------------------------------------------------------
// Timer3 Interrupt Service Routine (ISR)
//-----------------------------------------------------------------------------------
//
// A Timer3 interrupt indicates an SMBus SCL low timeout.
// The SMBus is disabled and re-enabled here
//
void Timer3_ISR (void) interrupt 14
{
   SMB0CN &= ~0x40;                          // Disable SMBus
   SMB0CN |= 0x40;                           // Re-enable SMBus
   TMR3CN &= ~0x80;                          // Clear Timer3 interrupt-pending flag
}