smbus_eeprom_f30x.c

c8051f的IIC读取eeprom,有很好的程序结构

   // Initiate SMBus Transfer
   STA = 1;
   while(SMB_BUSY);                          // Wait until data is read

   return retval;

}

//------------------------------------------------------------------------------------
// EEPROM_ReadArray ()
//------------------------------------------------------------------------------------
// Reads up to 256 data bytes from the EEPROM slave specified by the <EEPROM_ADDR> 
// constant.
//
void EEPROM_ReadArray (unsigned char* dest_addr, unsigned char src_addr,
                       unsigned char len)
{
   while (SMB_BUSY);                         // Wait for SMBus to be free.
   SMB_BUSY = 1;                             // Claim SMBus (set to busy)

   // Set SMBus ISR parameters
   TARGET = EEPROM_ADDR;                     // Set target slave address
   SMB_RW = WRITE;                           // A random read starts as a write
                                             // then changes to a read after
                                             // the repeated start is sent. The
                                             // ISR handles this switchover if
                                             // the <SMB_RANDOMREAD> bit is set.
   SMB_SENDWORDADDR = 1;                     // Send Word Address after Slave Address
   SMB_RANDOMREAD = 1;                       // Send a START after the word address
   SMB_ACKPOLL = 1;                          // Enable Acknowledge Polling

   // Specify the Incoming Data
   WORD_ADDR = src_addr;                     // Set the target address in the 
                                             // EEPROM's internal memory space

   pSMB_DATA_IN = (unsigned char*) dest_addr;// Set the the incoming data pointer


   SMB_DATA_LEN = len;                       // Specify to ISR that the next transfer
                                             // will contain <len> data bytes


   // Initiate SMBus Transfer
   STA = 1;
   while(SMB_BUSY);                          // Wait until data is read

}
//------------------------------------------------------------------------------------
// Initialization Routines
//------------------------------------------------------------------------------------

//------------------------------------------------------------------------------------
// SMBus_Init()
//------------------------------------------------------------------------------------
//
// SMBus configured as follows:
// - SMBus enabled
// - Slave mode disabled
// - Timer1 used as clock source. The maximum SCL frequency will be approximately
//   1/3 the Timer1 overflow rate
// - Setup and hold time extensions enabled
// - Free and SCL low timeout detection enabled
//
void SMBus_Init (void)
{
   SMB0CF = 0x5D;                            // Use Timer1 overflows as SMBus clock
                                             // source;
                                             // Disable slave mode;
                                             // Enable setup & hold time extensions;
                                             // Enable SMBus Free timeout detect;
                                             // Enable SCL low timeout detect;

   SMB0CF |= 0x80;                           // Enable SMBus;
}

//------------------------------------------------------------------------------------
// Timer2_Init()
//------------------------------------------------------------------------------------
//
// Timer2 configured for use by the SMBus low timeout detect feature as follows:
// - Timer2 in 16-bit auto-reload mode
// - SYSCLK/12 as Timer2 clock source
// - Timer2 reload registers loaded for a 25ms overflow period
// - Timer2 pre-loaded to overflow after 25ms
// - Timer2 enabled
//
void Timer2_Init (void)
{
   TMR2CN = 0x00;                            // Timer2 configured for 16-bit auto-
                                             // reload, low-byte interrupt disabled

   CKCON &= ~0x20;                           // Timer2 uses SYSCLK/12

   TMR2RL = -(SYSCLK/12/40);                 // Timer2 configured to overflow after
   TMR2 = TMR2RL;                            // ~25ms (for SMBus low timeout detect)

   TR2 = 1;                                  // Start Timer2
}

//------------------------------------------------------------------------------------
// Timer1_Init()
//------------------------------------------------------------------------------------
//
// Timer1 configured as the SMBus clock source as follows:
// - Timer1 in 8-bit auto-reload mode
// - SYSCLK / 12 as Timer1 clock source
// - Timer1 overflow rate => 3 * SMB_FREQUENCY
// - The maximum SCL clock rate will be ~1/3 the Timer1 overflow rate
// - Timer1 enabled
//
void Timer1_Init (void)
{
   CKCON &= ~0x13;                           // Timer1 clock source = SYSCLK / 12
   TMOD = 0x20;                              // Timer1 in 8-bit auto-reload mode

   TH1 = -(SYSCLK/SMB_FREQUENCY/12/3);       // Timer1 configured to overflow at 1/3
                                             // the rate defined by SMB_FREQUENCY

   TL1 = TH1;                                // Init Timer1

   TR1 = 1;                                  // Timer1 enabled
}

//------------------------------------------------------------------------------------
// PORT_Init
//------------------------------------------------------------------------------------
//
// Configure the Crossbar and GPIO ports.
// P0.0 - SDA
// P0.1 - SCL
// P0.2 -
// P0.3 - SW2
// P0.4 -
// P0.5 -
// P0.6 -
// P0.7 - C2D
//
void PORT_Init (void)
{
   XBR0 = 0x00;                              // No pins skipped
   XBR1 = 0x04;                              // Enable SMBus pins
   XBR2 = 0x40;                              // Enable crossbar and weak pull-ups

   P0MDIN = 0xFF;                            // All P0 pins in digital mode
   P0MDOUT = 0x00;                           // All P0 pins in open-drain output mode
   P0 = 0xFF;                                //
}

//------------------------------------------------------------------------------------
// SMBus Interrupt Service Routine (ISR)
//------------------------------------------------------------------------------------
//
// SMBus ISR state machine
// - Master only implementation - no slave or arbitration states defined
// - All incoming data is written starting at the global pointer <pSMB_DATA_IN>
// - All outgoing data is read from the global pointer <pSMB_DATA_OUT>
//
void SMBus_ISR (void) interrupt 6
{
   bit FAIL = 0;                             // Used by the ISR to flag failed
                                             // transfers

   static char i;                            // Used by the ISR to count the
                                             // number of data bytes sent or
                                             // received

   static bit SEND_START = 0;                // Send a start

   switch (SMB0CN & 0xF0)                    // Status vector
   {
      // Master Transmitter/Receiver: START condition transmitted.
      case SMB_MTSTA:
         SMB0DAT = TARGET;                   // Load address of the target slave
         SMB0DAT |= SMB_RW;                  // Load R/W bit
         STA = 0;                            // Manually clear START bit
         i = 0;                              // reset data byte counter
         break;

      // Master Transmitter: Data byte (or Slave Address) transmitted
      case SMB_MTDB:
         if (ACK)                            // Slave Address or Data Byte
         {                                   // Acknowledged?
            if (SEND_START)
            {
               STA = 1;
               SEND_START = 0;
               break;
            }
            if(SMB_SENDWORDADDR)             // Are we sending the word address?
            {
               SMB_SENDWORDADDR = 0;         // Clear flag
               SMB0DAT = WORD_ADDR;          // send word address

               if (SMB_RANDOMREAD)
               {
                  SEND_START = 1;            // send a START after the next ACK cycle
                  SMB_RW = READ;
               }

               break;
            }

            if (SMB_RW==WRITE)               // Is this transfer a WRITE?
            {

               if (i < SMB_DATA_LEN)         // Is there data to send?
               {
                  SMB0DAT = *pSMB_DATA_OUT;  // send data byte
                  pSMB_DATA_OUT++;           // increment data out pointer
                  i++;                       // increment number of bytes sent
               }
               else
               {
                 STO = 1;                    // set STO to terminte transfer
                 SMB_BUSY = 0;               // clear software busy flag
               }
            }
            else {}                          // If this transfer is a READ,
                                             // then take no action. Slave
                                             // address was transmitted. A
                                             // separate 'case' is defined
                                             // for data byte recieved.
         }
         else                                // If slave NACK,
         {
            if(SMB_ACKPOLL)
            {
               STA = 1;                      // Restart transfer
            }
            else
            {
               FAIL = 1;                     // Indicate failed transfer
            }                                // and handle at end of ISR
         }
         break;

      // Master Receiver: byte received
      case SMB_MRDB:
         if ( i < SMB_DATA_LEN )             // Is there any data remaining?
         {
            *pSMB_DATA_IN = SMB0DAT;         // Store received byte
            pSMB_DATA_IN++;                  // Increment data in pointer
            i++;                             // Increment number of bytes received
            ACK = 1;                         // Set ACK bit (may be cleared later
                                             // in the code)

         }

         if (i == SMB_DATA_LEN)              // This is the last byte
         {
            SMB_BUSY = 0;                    // Free SMBus interface
            ACK = 0;                         // Send NACK to indicate last byte
                                             // of this transfer
            STO = 1;                         // Send STOP to terminate transfer
         }

         break;

      default:
         FAIL = 1;                           // Indicate failed transfer
                                             // and handle at end of ISR
         break;
   }

   if (FAIL)                                 // If the transfer failed,
   {
      SMB0CN &= ~0x40;                       // Reset communication
      SMB0CN |= 0x40;
      SMB_BUSY = 0;                          // Free SMBus
   }

   SI=0;                                     // clear interrupt flag
}

//------------------------------------------------------------------------------------
// Timer2 Interrupt Service Routine (ISR)
//------------------------------------------------------------------------------------
//
// A Timer2 interrupt indicates an SMBus SCL low timeout.
// The SMBus is disabled and re-enabled here
//
void Timer2_ISR (void) interrupt 5
{
   SMB0CN &= ~0x40;                          // Disable SMBus
   SMB0CN |= 0x40;                           // Re-enable SMBus
   TF2H = 0;                                 // Clear Timer2 interrupt-pending flag
}