lcd_init.v

基于ＡＬＴＥＲＡ公司的ＤＥ２的ＬＣＤ显示程序

/*-------------------------------------------------
-------------LCD_init.v-----------------------------
all rights reserved by the author.
function:write lcd1602,no read
author:XT
email: [e-mail]
qq：360303839
date:060109

1602液晶内部显示地址：
 1  2  3  4  5  6  7  8  9  10 11 12 13 14 15 16
 ------------------------------------------------
|00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f |row1
|40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f |row2
 ------------------------------------------------
要显示字符时要先输入显示字符地址，也就是告诉模块在哪里显示字符
比如第二行第一个字符的地址是40H，那么是否直接写入40H就可以将
光标定位在第二行第一个字符的位置呢？这样不行，因为写入显示地址
时要求最高位D7恒定为高电平1所以实际写入的数据应该是
01000000B（40H)[phone]B(80H)=11000000B(C0H)

初始化过程：
1> 延时15ms；2> 写指令38H（不检测忙）
3> 延时5ms； 4> 写指令38H（不检测忙）
5> 延时5ms； 6> 写指令38H（不检测忙）
7> 以下指令均检测忙信号(在本模块中均不检测)
8> 写指令38H：显示模式设置
9> 写指令08H：显示关闭
10>写指令01H：显示清屏
11>写指令06H：显示光标移动设置
12>写指令0cH：显示开及光标设置
本模块用下列初始化过程：
1.上电延时>=15ms； 2.写0x00；3.写指令38H（"Function Set" in 8 bits mode）；
4.延时>=5ms； 5.写0x00；6.写指令0FH（"Display ON" with cursors ON）；
7.延时>=5ms;  8.写0x00；9.写指令01H("Clear Display").

---------------------------------------------------------------------
Operation of the HD44780 
Registers 
The HD44780 has two 8 bit registers, an instruction register (IR) 
and a data register (DR).
 
The IR stores instruction codes such as display clear and cursor shift, 
and address information for display data RAM (DD RAM) and character generator
 RAM (CG RAM). The IR can be written from the MPU but not read by the MPU. 

The DR temporarily stores data to be written into the DD RAM or the CG RAM and
 data to be read out from the DD RAM or the CG RAM. Data written into the DR 
 from the MPU is automatically written into the DD RAM or the CG RAM by internal 
 operation. The DR is also used for data storage when reading from the DD RAM 
 or the CG RAM. When address information is written into the IR, data is read 
 into the DR from the DD RAM or the CG RAM by internal operation. Data transfer 
 to the MPU is then completed by the MPU reading DR. After the MPU reads the DR, 
 data in the DD RAM or CG RAM at the next address is sent to the DR for the next 
 read from the MPU. Register selector (RS) signals make their selection from 
 these two registers. 
----------------------------------------------------------------------

Register selection 

RS  R/W  Enable  Operation                     
==  ===  ======  =========                     
 0   0   H,H->L  IR write as internal operation
                          (Display clear, etc.)
 0   1     H     Read busy flag (DB7) and      
                      address counter (DB0-DB6)
 1   0   H,H->L  DR write as internal operation
                       (DR to DD RAM or CG RAM)
 1   1     H     DR read  as internal operation
                       (DD RAM or CG RAM to DR)
-------------------------------------------------------------------------
Busy Flag 
When the busy flag is "1", the HD44780 is in the internal operation mode, 
and the next instruction will not be accepted. As the Register selection 
table above shows, the busy flag is output to DB7 when RS = 0 and R/W = 1. 
The next instruction must be written after ensuring that the busy flag is "0".
 
Address counter (AC) 
The address counter (AC) assigns addresses to DD and CG RAMs. When an 
 instruction for address is written in IR, the address information is sent
 from IR to AC. Selection of either DD or CG RAM is also determined 
 concurrently by the instruction. 

After writing into (or reading from) DD or CG RAM display data, AC is 
automatically incremented or decremented by 1. AC contents are output
as DB0-DB6 when RS = 0 and R/W = 1, as shown in the Register selection 
table above. 

Display Data RAM (DD RAM) 
The display data RAM (DD RAM) stores display data represented in 8-bit
 character codes. Its capacity is 80 x 8 bits, or 80 characters. On 
 displays with fewer than 80 characters, any DD RAM that is not used 
 for display can be used as a general data RAM. The relationship 
 between DD RAM addresses and positions on the liquid crystal display
 are shown below. The DD RAM address is set in the Address Counter (AC) 
 and is expressed in hexadecimal. 

DD RAM addresses for a 40 character x 2 line display 
 
With the 40 character x 2 line display provided by the LM018L, when a 
display shift is performed the display will "wrap round". A Left shift 
will cause the character previously at display position 1 to "drop off" 
the left end and reappear at display position 40. A Right shift will cause 
the character previously at display position 40 to "drop off" the right end 
and reappear at display position 1. 

Character Generator ROM (CG ROM) 
The Character Generator ROM generates 5 x 7 dot or 5 x 10 dot character 
patterns from 8-bit character codes. It contains 192 5 x 7 dot character 
patterns and 192 5 x 10 dot character patterns. 

Character Generator RAM (CG RAM) 
The Character Generator RAM is RAM with which the user can redefine 
character patterns in software. With 5 x 7 dots, 8 user-defined character 
patterns can be stored and with 5 x 10 dots, 4 user-defined character patterns 
can be stored. 
-------------------------------------------------------------------------------
Initialisation of the HD44780 
Initialising by internal reset circuit 

HD44780 Instruction Set 

   Instruction                                 Code

                             RS  R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
                             ==  === === === === === === === === ===
Clear Display                 0   0   0   0   0   0   0   0   0   1

Return Home                   0   0   0   0   0   0   0   0   1   *

Entry Mode Set                0   0   0   0   0   0   0   1  I/D  S

Display ON/OFF                0   0   0   0   0   0   1   D   C   B

Cursor and Display Shift      0   0   0   0   0   1  S/C R/L  *   *

Function Set                  0   0   0   0   1   DL  N   F   *   *

Set CG RAM address            0   0   0   1   A   A   A   A   A   A

Set DD RAM address            0   0   1   A   A   A   A   A   A   A

Read busy flag and address    0   1   BF  A   A   A   A   A   A   A

Write data to CG or DD RAM    1   0   D   D   D   D   D   D   D   D

Read data from CG or DD RAM   1   1   D   D   D   D   D   D   D   D

Notes 
* means 0 or 1 have no effect 

Where execution times are given as A / B 
A applies for 1/8 duty or 1/11 duty (1 display line) 
B applies for 1/16 duty (2 display lines) 
-----------------------------------------------------------------------
The HD44780 automatically initialises (resets) when power is 
 turned on using the internal reset circuit. The following 
 instructions are executed in initialisation. The busy flag (BF)
 is kept in busy state until initialisation ends. The busy state
 (BF=1) is 10ms after Vcc rises to 4.5volts. 

1. Display clear

2. Function set ..... DL = 1: 8 bit interface
                       N = 0: 1 line display
                       F = 0: 5 x 7 dot character font

3. Display ON/OFF ...  D = 0: Display OFF
                       C = 0: Cursor OFF
                       B = 0: Blink OFF

4. Entry mode set .. I/D = 1: +1 (increment)
                       S = 0: No shift

5. Write DD RAM
   When the rise time of power supply (0.2 -> 4.5) is out
   of the range 0.1ms - 10ms, or when the low level width
   of power OFF (less than 0.2) is less than 1ms, the
   internal reset circuit will not operate normally.
   In this case, initialisation will not be performed
   normally. Initialise by instruction, as detailed below.

If the power supply conditions for correctly operating the internal reset 
circuit are not met, initialisation by instruction is required. 
----------------------------------------------------------------------------
Initialising by instruction 

When interface is 8-bits wide 


              [Power ON]

       [  Wait more than 15ms  ]
       [after Vdd rises to 4.5v]

RS  R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  Can't check BF before this instruction
 0   0   0   0   1   1   *   *   *   *   Function set (8-bit interface)

        [Wait more than 4.1ms]

RS  R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  Can't check BF before this instruction
 0   0   0   0   1   1   *   *   *   *   Function set (8-bit interface)