fads.c

u-boot-1.1.6 源码包

/* ------------------------------------------------------------------------- */
#else  /* !SDRAM_ALT_INIT_SEQUENCE */
/* ------------------------------------------------------------------------- */

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
# define MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
# define MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
# define MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
# define MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */

/*
 * MxMR settings for SDRAM
 */

/* 8 column SDRAM */
# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT)  | MBMR_PTBE  |   \
			MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
			MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
/* 9 column SDRAM */
# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT)  | MBMR_PTAE  |   \
			MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
			MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)

static int _initsdram(uint base, uint noMbytes)
{
	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));

	memctl->memc_mptpr = MPTPR_2BK_4K;
	memctl->memc_mbmr  = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */

	/* map CS 4 */
	memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
	memctl->memc_br4 = SDRAM_BR4VALUE | base;

	/* Perform SDRAM initilization */
# ifdef UPM_NOP_ADDR    /* not currently in UPM table */
	/* step 1: nop */
	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
			   MCR_MLCF(0) | UPM_NOP_ADDR;
# endif

	/* step 2: delay */
	udelay(200);

# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */
	/* step 3: precharge */
	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
			   MCR_MLCF(4) | UPM_PRECHARGE_ADDR;
# endif

	/* step 4: refresh */
	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
			   MCR_MLCF(2) | UPM_REFRESH_ADDR;

	/*
	 * note: for some reason, the UPM values we are using include
	 * precharge with MRS
	 */

	/* step 5: mrs */
	memctl->memc_mar = 0x00000088;
	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
			   MCR_MLCF(1) | UPM_MRS_ADDR;

# ifdef UPM_NOP_ADDR
	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
			   MCR_MLCF(0) | UPM_NOP_ADDR;
# endif
	/*
	 * Enable refresh
	 */

	memctl->memc_mbmr |= MBMR_PTBE;
	return 0;
}
#endif  /* !SDRAM_ALT_INIT_SEQUENCE */

/* ------------------------------------------------------------------------- */

static void _sdramdisable(void)
{
	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_br4 = 0x00000000;

	/* maybe we should turn off upmb here or something */
}

/* ------------------------------------------------------------------------- */

static int initsdram(uint base, uint *noMbytes)
{
	uint m = CFG_SDRAM_SIZE>>20;

	/* _initsdram needs access to sdram */
	*((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */

	if(!_initsdram(base, m))
	{
	        *noMbytes += m;
		return 0;
	}
	else
	{
		*((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */

		_sdramdisable();

		return -1;
	}
}

#endif /* CONFIG_FADS */

/* ========================================================================= */

long int initdram (int board_type)
{
	uint sdramsz = 0;	/* size of sdram in Mbytes */
	uint base = 0;		/* base of dram in bytes */
	uint m = 0;		/* size of dram in Mbytes */
#ifndef CONFIG_MPC885ADS
	uint k, s;
#endif

#ifdef CONFIG_FADS
	if (!initsdram (0x00000000, &sdramsz)) {
		base = sdramsz << 20;
		printf ("(%u MB SDRAM) ", sdramsz);
	}
#endif
#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
	k = (*((uint *) BCSR2) >> 23) & 0x0f;

	switch (k & 0x3) {
		/* "MCM36100 / MT8D132X" */
	case 0x00:
		m = 4;
		break;

		/* "MCM36800 / MT16D832X" */
	case 0x01:
		m = 32;
		break;
		/* "MCM36400 / MT8D432X" */
	case 0x02:
		m = 16;
		break;
		/* "MCM36200 / MT16D832X ?" */
	case 0x03:
		m = 8;
		break;

	}

	switch (k >> 2) {
	case 0x02:
		k = 70;
		break;

	case 0x03:
		k = 60;
		break;

	default:
		printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
		k = 70;
	}

#ifdef CONFIG_FADS
	/* the FADS is missing this bit, all rams treated as non-edo */
	s = 0;
#else
	s = (*((uint *) BCSR2) >> 27) & 0x01;
#endif

	if (!_draminit (base, m, s, k)) {
		printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : "");
	} else {
		_dramdisable ();
		m = 0;
	}
#endif /* !CONFIG_MPC885ADS */
	m += sdramsz;				/* add sdram size to total */

	return (m << 20);
}

/* ------------------------------------------------------------------------- */

int testdram (void)
{
    /* TODO: XXX XXX XXX */
    printf ("test: 16 MB - ok\n");

    return (0);
}

/* ========================================================================= */

/*
 * Check Board Identity:
 */

#if defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD)
static void checkdboard(void)
{
	/* get db type from BCSR 3 */
	uint k = (*((uint *)BCSR3) >> 24) & 0x3f;

	puts (" with db ");

	switch(k) {
	case 0x03 :
		puts ("MPC823");
		break;
	case 0x20 :
		puts ("MPC801");
		break;
	case 0x21 :
		puts ("MPC850");
		break;
	case 0x22 :
		puts ("MPC821, MPC860 / MPC860SAR / MPC860T");
		break;
	case 0x23 :
		puts ("MPC860SAR");
		break;
	case 0x24 :
	case 0x2A :
		puts ("MPC860T");
		break;
	case 0x3F :
		puts ("MPC850SAR");
		break;
	default : printf("0x%x", k);
	}
}
#endif	/* defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) */

int checkboard (void)
{
#if   defined(CONFIG_MPC86xADS)
	puts ("Board: MPC86xADS\n");
#elif defined(CONFIG_MPC885ADS)
	puts ("Board: MPC885ADS\n");
#else /* Only old ADS/FADS have got revision ID in BCSR3 */
	uint r =  (((*((uint *) BCSR3) >> 23) & 1) << 3)
		| (((*((uint *) BCSR3) >> 19) & 1) << 2)
		| (((*((uint *) BCSR3) >> 16) & 3));

	puts ("Board: ");
#if defined(CONFIG_FADS)
	puts ("FADS");
	checkdboard ();
#else
	puts ("ADS");
#endif

	puts (" rev ");

	switch (r) {
#if defined(CONFIG_ADS)
	case 0x00:
		puts ("ENG - this board sucks, check the errata, not supported\n");
		return -1;
	case 0x01:
		puts ("PILOT - warning, read errata \n");
		break;
	case 0x02:
		puts ("A - warning, read errata \n");
		break;
	case 0x03:
		puts ("B\n");
		break;
#else  /* FADS */
	case 0x00:
		puts ("ENG\n");
		break;
	case 0x01:
		puts ("PILOT\n");
		break;
#endif /* CONFIG_ADS */
	default:
		printf ("unknown (0x%x)\n", r);
		return -1;
	}
#endif /* CONFIG_MPC86xADS */

	return 0;
}

/* ========================================================================= */

#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)

#ifdef CFG_PCMCIA_MEM_ADDR
volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
#endif

int pcmcia_init(void)
{
	volatile pcmconf8xx_t	*pcmp;
	uint v, slota = 0, slotb = 0;

	/*
	** Enable the PCMCIA for a Flash card.
	*/
	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));

#if 0
	pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
	pcmp->pcmc_por0 = 0xc00ff05d;
#endif

	/* Set all slots to zero by default. */
	pcmp->pcmc_pgcra = 0;
	pcmp->pcmc_pgcrb = 0;
#ifdef CONFIG_PCMCIA_SLOT_A
	pcmp->pcmc_pgcra = 0x40;
#endif
#ifdef CONFIG_PCMCIA_SLOT_B
	pcmp->pcmc_pgcrb = 0x40;
#endif

	/* enable PCMCIA buffers */
	*((uint *)BCSR1) &= ~BCSR1_PCCEN;

	/* Check if any PCMCIA card is plugged in. */

#ifdef CONFIG_PCMCIA_SLOT_A
	slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
#endif
#ifdef CONFIG_PCMCIA_SLOT_B
	slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
#endif

	if (!(slota || slotb)) {
		printf("No card present\n");
		pcmp->pcmc_pgcra = 0;
		pcmp->pcmc_pgcrb = 0;
		return -1;
	}
	else
		printf("Card present (");

	v = 0;

	/* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
	**
	** Paolo - Yes, but i have to insert some 3.3V card in that slot on
	**	   my FADS... :-)
	*/

#if defined(CONFIG_MPC86x)
	switch ((pcmp->pcmc_pipr >> 30) & 3)
#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
	switch ((pcmp->pcmc_pipr >> 14) & 3)
#endif
	{
	case 0x03 :
		printf("5V");
		v = 5;
		break;
	case 0x01 :
		printf("5V and 3V");
#ifdef CONFIG_FADS
		v = 3; /* User lower voltage if supported! */
#else
		v = 5;
#endif
		break;
	case 0x00 :
		printf("5V, 3V and x.xV");
#ifdef CONFIG_FADS
		v = 3; /* User lower voltage if supported! */
#else
		v = 5;
#endif
		break;
	}

	switch (v) {
#ifdef CONFIG_FADS
	case 3:
		printf("; using 3V");
		/*
		** Enable 3 volt Vcc.
		*/
		*((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
		*((uint *)BCSR1) |= BCSR1_PCCVCC0;
		break;
#endif
	case 5:
		printf("; using 5V");
#ifdef CONFIG_ADS
		/*
		** Enable 5 volt Vcc.
		*/
		*((uint *)BCSR1) &= ~BCSR1_PCCVCCON;
#endif
#ifdef CONFIG_FADS
		/*
		** Enable 5 volt Vcc.
		*/
		*((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
		*((uint *)BCSR1) |= BCSR1_PCCVCC1;
#endif
		break;

	default:
		*((uint *)BCSR1) |= BCSR1_PCCEN;  /* disable pcmcia */

		printf("; unknown voltage");
		return -1;
	}
	printf(")\n");
	/* disable pcmcia reset after a while */

	udelay(20);

#ifdef CONFIG_PCMCIA_SLOT_A
	pcmp->pcmc_pgcra = 0;
#endif
#ifdef CONFIG_PCMCIA_SLOT_B
	pcmp->pcmc_pgcrb = 0;
#endif

	/* If you using a real hd you should give a short
	* spin-up time. */
#ifdef CONFIG_DISK_SPINUP_TIME
	udelay(CONFIG_DISK_SPINUP_TIME);
#endif

	return 0;
}

#endif	/* CFG_CMD_PCMCIA */

/* ========================================================================= */

#ifdef CFG_PC_IDE_RESET

void ide_set_reset(int on)
{
	volatile immap_t *immr = (immap_t *)CFG_IMMR;

	/*
	 * Configure PC for IDE Reset Pin
	 */
	if (on) {		/* assert RESET */
		immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
	} else {		/* release RESET */
		immr->im_ioport.iop_pcdat |=   CFG_PC_IDE_RESET;
	}

	/* program port pin as GPIO output */
	immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
	immr->im_ioport.iop_pcso  &= ~(CFG_PC_IDE_RESET);
	immr->im_ioport.iop_pcdir |=   CFG_PC_IDE_RESET;
}

#endif	/* CFG_PC_IDE_RESET */