mpc8260ads.c

u-boot-1.1.6 源码包

/*
 * (C) Copyright 2001-2003
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * Modified during 2001 by
 * Advanced Communications Technologies (Australia) Pty. Ltd.
 * Howard Walker, Tuong Vu-Dinh
 *
 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, [e-mail]
 * Added support for the 16M dram simm on the 8260ads boards
 *
 * (C) Copyright 2003-2004 Arabella Software Ltd.
 * Yuli Barcohen <[e-mail]>
 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
 *
 * Copyright (c) 2005 MontaVista Software, Inc.
 * Vitaly Bordug <[e-mail]>
 * Added support for PCI.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include <asm/m8260_pci.h>
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
#ifdef CONFIG_PCI
#include <pci.h>
#endif

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {	/*	      conf      ppar psor pdir podr pdat */
	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
	/* PA9  */ { 0,          0,   0,   0,   0,   0 }, /* PA9 */
	/* PA8  */ { 0,          0,   0,   0,   0,   0 }, /* PA8 */
	/* PA7  */ { 0,          0,   0,   1,   0,   0 }, /* PA7 */
	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
	/* PA5  */ { 0,          0,   0,   1,   0,   0 }, /* PA5 */
	/* PA4  */ { 0,          0,   0,   1,   0,   0 }, /* PA4 */
	/* PA3  */ { 0,          0,   0,   1,   0,   0 }, /* PA3 */
	/* PA2  */ { 0,          0,   0,   1,   0,   0 }, /* PA2 */
	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
	/* PA0  */ { 0,          0,   0,   1,   0,   0 }  /* PA0 */
    },

    /* Port B configuration */
    {   /*	      conf      ppar psor pdir podr pdat */
	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER */
	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV */
	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN */
	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER */
	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL */
	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS */
	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
	/* PB17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_DIV */
	/* PB16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_ERR */
	/* PB15 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_ERR */
	/* PB14 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_EN */
	/* PB13 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:COL */
	/* PB12 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:CRS */
	/* PB11 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
	/* PB10 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
	/* PB9  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
	/* PB8  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
	/* PB7  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
	/* PB6  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
	/* PB5  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
	/* PB4  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
    },

    /* Port C */
    {   /*	      conf      ppar psor pdir podr pdat */
	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
	/* PC22 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Tx Clock (CLK10) */
	/* PC21 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Rx Clock (CLK11) */
	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
#if CONFIG_ADSTYPE == CFG_8272ADS
	/* PC19 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
	/* PC18 */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
	/* PC17 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK15) */
	/* PC16 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK16) */
#else
	/* PC19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK13) */
	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK14) */
	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16 */
#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
#if CONFIG_ADSTYPE == CFG_8272ADS
	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
#else
	/* PC10 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
	/* PC9  */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8 */
	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7 */
	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6 */
	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5 */
	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4 */
	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3 */
	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2 */
	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1 */
	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0 */
    },

    /* Port D */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* PD29 */
	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    }
};

void reset_phy (void)
{
	vu_long *bcsr = (vu_long *)CFG_BCSR;

	/* Reset the PHY */
#if CFG_PHY_ADDR == 0
	bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
	udelay(2);
	bcsr[1] |=  FETH1_RST;
#else
	bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
	udelay(2);
	bcsr[3] |=  FETH2_RST;
#endif /* CFG_PHY_ADDR == 0 */
	udelay(1000);
#ifdef CONFIG_MII
#if CONFIG_ADSTYPE >= CFG_PQ2FADS
	/*
	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
	 * Enable autonegotiation.
	 */
	bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#else
	/*
	 * Ethernet PHY is configured (by means of configuration pins)
	 * to work at 10Mb/s only. We reconfigure it using MII
	 * to advertise all capabilities, including 100Mb/s, and
	 * restart autonegotiation.
	 */

	/* Advertise all capabilities */
	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);

	/* Do not bypass Rx/Tx (de)scrambler */
	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR,  0x0000);

	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
#endif /* CONFIG_MII */
}

#ifdef CONFIG_PCI
typedef struct pci_ic_s {
	unsigned long pci_int_stat;
	unsigned long pci_int_mask;
}pci_ic_t;
#endif

int board_early_init_f (void)
{
	vu_long *bcsr = (vu_long *)CFG_BCSR;