codec.c

u-boot-1.1.6 源码包

/*
 * CODEC
 */

#include <common.h>
#include <post.h>

#include "mpc8xx.h"

/***********************************************/

#define MAX_DUSLIC	4

#define NUM_CHANNELS	2
#define MAX_SLICS	(MAX_DUSLIC * NUM_CHANNELS)

/***********************************************/

#define SOP_READ_CH_0		0xC4  /* Read SOP Register for Channel A  */
#define SOP_READ_CH_1		0xCC  /* Read SOP Register for Channel B  */
#define SOP_WRITE_CH_0		0x44  /* Write SOP Register for Channel A */
#define SOP_WRITE_CH_1		0x4C  /* Write SOP Register for Channel B */

#define COP_READ_CH_0		0xC5
#define COP_READ_CH_1		0xCD
#define COP_WRITE_CH_0		0x45
#define COP_WRITE_CH_1		0x4D

#define POP_READ_CH_0		0xC6
#define POP_READ_CH_1		0xCE
#define POP_WRITE_CH_0		0x46
#define POP_WRITE_CH_1		0x4E

#define RST_CMD_DUSLIC_CHIP	0x40  /* OR 0x48 */
#define RST_CMD_DUSLIC_CH_A	0x41
#define RST_CMD_DUSLIC_CH_B	0x49

#define PCM_RESYNC_CMD_CH_A	0x42
#define PCM_RESYNC_CMD_CH_B	0x4A

#define ACTIVE_HOOK_LEV_4	0
#define ACTIVE_HOOK_LEV_12	1

#define SLIC_P_NORMAL		0x01

/************************************************/

#define CODSP_WR	0x00
#define CODSP_RD	0x80
#define CODSP_OP	0x40
#define CODSP_ADR(x)	(((unsigned char)(x) & 7) << 3)
#define CODSP_M(x)	((unsigned char)(x) & 7)
#define CODSP_CMD(x)	((unsigned char)(x) & 7)

/************************************************/

/* command indication ops */
#define CODSP_M_SLEEP_PWRDN	7
#define CODSP_M_PWRDN_HIZ	0
#define CODSP_M_ANY_ACT		2
#define CODSP_M_RING		5
#define CODSP_M_ACT_MET		6
#define CODSP_M_GND_START	4
#define CODSP_M_RING_PAUSE	1

/* single byte commands */
#define CODSP_CMD_SOFT_RESET	CODSP_CMD(0)
#define CODSP_CMD_RESET_CH	CODSP_CMD(1)
#define CODSP_CMD_RESYNC	CODSP_CMD(2)

/* two byte commands */
#define CODSP_CMD_SOP		CODSP_CMD(4)
#define CODSP_CMD_COP		CODSP_CMD(5)
#define CODSP_CMD_POP		CODSP_CMD(6)

/************************************************/

/* read as 4-bytes */
#define CODSP_INTREG_INT_CH	0x80000000
#define CODSP_INTREG_HOOK	0x40000000
#define CODSP_INTREG_GNDK	0x20000000
#define CODSP_INTREG_GNDP	0x10000000
#define CODSP_INTREG_ICON	0x08000000
#define CODSP_INTREG_VRTLIM	0x04000000
#define CODSP_INTREG_OTEMP	0x02000000
#define CODSP_INTREG_SYNC_FAIL	0x01000000
#define CODSP_INTREG_LM_THRES	0x00800000
#define CODSP_INTREG_READY	0x00400000
#define CODSP_INTREG_RSTAT	0x00200000
#define CODSP_INTREG_LM_OK	0x00100000
#define CODSP_INTREG_IO4_DU	0x00080000
#define CODSP_INTREG_IO3_DU	0x00040000
#define CODSP_INTREG_IO2_DU	0x00020000
#define CODSP_INTREG_IO1_DU	0x00010000
#define CODSP_INTREG_DTMF_OK	0x00008000
#define CODSP_INTREG_DTMF_KEY4	0x00004000
#define CODSP_INTREG_DTMF_KEY3	0x00002000
#define CODSP_INTREG_DTMF_KEY2	0x00001000
#define CODSP_INTREG_DTMF_KEY1	0x00000800
#define CODSP_INTREG_DTMF_KEY0	0x00000400
#define CODSP_INTREG_UTDR_OK	0x00000200
#define CODSP_INTREG_UTDX_OK	0x00000100
#define CODSP_INTREG_EDSP_FAIL	0x00000080
#define CODSP_INTREG_CIS_BOF	0x00000008
#define CODSP_INTREG_CIS_BUF	0x00000004
#define CODSP_INTREG_CIS_REQ	0x00000002
#define CODSP_INTREG_CIS_ACT	0x00000001

/************************************************/

/* ======== SOP REG ADDRESSES =======*/

#define REVISION_ADDR		0x00
#define PCMC1_ADDR		0x05
#define XCR_ADDR		0x06
#define INTREG1_ADDR		0x07
#define INTREG2_ADDR		0x08
#define INTREG3_ADDR		0x09
#define INTREG4_ADDR		0x0A
#define LMRES1_ADDR		0x0D
#define MASK_ADDR		0x11
#define IOCTL3_ADDR		0x14
#define BCR1_ADDR		0x15
#define BCR2_ADDR		0x16
#define BCR3_ADDR		0x17
#define BCR4_ADDR		0x18
#define BCR5_ADDR		0x19
#define DSCR_ADDR		0x1A
#define LMCR1_ADDR		0x1C
#define LMCR2_ADDR		0x1D
#define LMCR3_ADDR		0x1E
#define OFR1_ADDR		0x1F
#define PCMR1_ADDR		0x21
#define PCMX1_ADDR		0x25
#define TSTR3_ADDR		0x2B
#define TSTR4_ADDR		0x2C
#define TSTR5_ADDR		0x2D

/* ========= POP REG ADDRESSES ========*/

#define CIS_DAT_ADDR		0x00

#define LEC_LEN_ADDR		0x3A
#define LEC_POWR_ADDR		0x3B
#define LEC_DELP_ADDR		0x3C
#define LEC_DELQ_ADDR		0x3D
#define LEC_GAIN_XI_ADDR	0x3E
#define LEC_GAIN_RI_ADDR	0x3F
#define LEC_GAIN_XO_ADDR	0x40
#define LEC_RES_1_ADDR		0x41
#define LEC_RES_2_ADDR		0x42

#define NLP_POW_LPF_ADDR	0x30
#define NLP_POW_LPS_ADDR	0x31
#define NLP_BN_LEV_X_ADDR	0x32
#define NLP_BN_LEV_R_ADDR	0x33
#define NLP_BN_INC_ADDR		0x34
#define NLP_BN_DEC_ADDR		0x35
#define NLP_BN_MAX_ADDR		0x36
#define NLP_BN_ADJ_ADDR		0x37
#define NLP_RE_MIN_ERLL_ADDR	0x38
#define NLP_RE_EST_ERLL_ADDR	0x39
#define NLP_SD_LEV_X_ADDR	0x3A
#define NLP_SD_LEV_R_ADDR	0x3B
#define NLP_SD_LEV_BN_ADDR	0x3C
#define NLP_SD_LEV_RE_ADDR	0x3D
#define NLP_SD_OT_DT_ADDR	0x3E
#define NLP_ERL_LIN_LP_ADDR	0x3F
#define NLP_ERL_LEC_LP_ADDR	0x40
#define NLP_CT_LEV_RE_ADDR	0x41
#define NLP_CTRL_ADDR		0x42

#define UTD_CF_H_ADDR		0x4B
#define UTD_CF_L_ADDR		0x4C
#define UTD_BW_H_ADDR		0x4D
#define UTD_BW_L_ADDR		0x4E
#define UTD_NLEV_ADDR		0x4F
#define UTD_SLEV_H_ADDR		0x50
#define UTD_SLEV_L_ADDR		0x51
#define UTD_DELT_ADDR		0x52
#define UTD_RBRK_ADDR		0x53
#define UTD_RTIME_ADDR		0x54
#define UTD_EBRK_ADDR		0x55
#define UTD_ETIME_ADDR		0x56

#define DTMF_LEV_ADDR		0x30
#define DTMF_TWI_ADDR		0x31
#define DTMF_NCF_H_ADDR		0x32
#define DTMF_NCF_L_ADDR		0x33
#define DTMF_NBW_H_ADDR		0x34
#define DTMF_NBW_L_ADDR		0x35
#define DTMF_GAIN_ADDR		0x36
#define DTMF_RES1_ADDR		0x37
#define DTMF_RES2_ADDR		0x38
#define DTMF_RES3_ADDR		0x39

#define CIS_LEV_H_ADDR		0x43
#define CIS_LEV_L_ADDR		0x44
#define CIS_BRS_ADDR		0x45
#define CIS_SEIZ_H_ADDR		0x46
#define CIS_SEIZ_L_ADDR		0x47
#define CIS_MARK_H_ADDR		0x48
#define CIS_MARK_L_ADDR		0x49
#define CIS_LEC_MODE_ADDR	0x4A

/*=====================================*/

#define HOOK_LEV_ACT_START_ADDR 0x89
#define RO1_START_ADDR		0x70
#define RO2_START_ADDR		0x95
#define RO3_START_ADDR		0x96

#define TG1_FREQ_START_ADDR	0x38
#define TG1_GAIN_START_ADDR	0x39
#define TG1_BANDPASS_START_ADDR 0x3B
#define TG1_BANDPASS_END_ADDR	0x3D

#define TG2_FREQ_START_ADDR	0x40
#define TG2_GAIN_START_ADDR	0x41
#define TG2_BANDPASS_START_ADDR 0x43
#define TG2_BANDPASS_END_ADDR	0x45

/*====================================*/

#define PCM_HW_B		0x80
#define PCM_HW_A		0x00
#define PCM_TIME_SLOT_0		0x00   /*  Byte 0 of PCM Frame (by default is assigned to channel A ) */
#define PCM_TIME_SLOT_1		0x01   /*  Byte 1 of PCM Frame (by default is assigned to channel B ) */
#define PCM_TIME_SLOT_4		0x04   /*  Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */

#define	 RX_LEV_ADDR	0x28
#define	 TX_LEV_ADDR	0x30
#define	 Ik1_ADDR	0x83

#define	 AR_ROW		3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct	*/
#define	 AX_ROW		6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct	*/
#define	 DCF_ROW	0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */

/* Mark the start byte of Duslic parameters that we use with configurator */
#define	 Ik1_START_BYTE		3
#define	 RX_LEV_START_BYTE	0
#define	 TX_LEV_START_BYTE	0

/************************************************/

#define INTREG4_CIS_ACT		(1 << 0)

#define BCR1_SLEEP		0x20
#define BCR1_REVPOL		0x10
#define BCR1_ACTR		0x08
#define BCR1_ACTL		0x04
#define BCR1_SLIC_MASK		0x03

#define BCR2_HARD_POL_REV	0x40
#define BCR2_TTX		0x20
#define BCR2_TTX_12K		0x10
#define BCR2_HIMAN		0x08
#define BCR2_PDOT		0x01

#define BCR3_PCMX_EN		(1 << 4)

#define BCR5_DTMF_EN		(1 << 0)
#define BCR5_DTMF_SRC		(1 << 1)
#define BCR5_LEC_EN		(1 << 2)
#define BCR5_LEC_OUT		(1 << 3)
#define BCR5_CIS_EN		(1 << 4)
#define BCR5_CIS_AUTO		(1 << 5)
#define BCR5_UTDX_EN		(1 << 6)
#define BCR5_UTDR_EN		(1 << 7)

#define DSCR_TG1_EN		(1 << 0)
#define DSCR_TG2_EN		(1 << 1)
#define DSCR_PTG		(1 << 2)
#define DSCR_COR8		(1 << 3)
#define DSCR_DG_KEY(x)		(((x) & 0x0F) << 4)

#define CIS_LEC_MODE_CIS_V23	(1 << 0)
#define CIS_LEC_MODE_CIS_FRM	(1 << 1)
#define CIS_LEC_MODE_NLP_EN	(1 << 2)
#define CIS_LEC_MODE_UTDR_SUM	(1 << 4)
#define CIS_LEC_MODE_UTDX_SUM	(1 << 5)
#define CIS_LEC_MODE_LEC_FREEZE (1 << 6)
#define CIS_LEC_MODE_LEC_ADAPT	(1 << 7)

#define TSTR4_COR_64		(1 << 5)

#define TSTR3_AC_DLB_8K		(1 << 2)
#define TSTR3_AC_DLB_32K	(1 << 3)
#define TSTR3_AC_DLB_4M		(1 << 5)


#define LMCR1_TEST_EN		(1 << 7)
#define LMCR1_LM_EN		(1 << 6)
#define LMCR1_LM_THM		(1 << 5)
#define LMCR1_LM_ONCE		(1 << 2)
#define LMCR1_LM_MASK		(1 << 1)

#define LMCR2_LM_RECT			(1 << 5)
#define LMCR2_LM_SEL_VDD		0x0D
#define LMCR2_LM_SEL_IO3		0x0A
#define LMCR2_LM_SEL_IO4		0x0B
#define LMCR2_LM_SEL_IO4_MINUS_IO3	0x0F

#define LMCR3_RTR_SEL		(1 << 6)

#define LMCR3_RNG_OFFSET_NONE	0x00
#define LMCR3_RNG_OFFSET_1	0x01
#define LMCR3_RNG_OFFSET_2	0x02
#define LMCR3_RNG_OFFSET_3	0x03

#define TSTR5_DC_HOLD		(1 << 3)

/************************************************/

#define TARGET_ONHOOK_BATH_x100		4600	/* 46.0 Volt */
#define TARGET_ONHOOK_BATL_x100		2500	/* 25.0 Volt */
#define TARGET_V_DIVIDER_RATIO_x100	21376L	/* (R1+R2)/R2 = 213.76 */
#define DIVIDER_RATIO_ACCURx100		(22 * 100)
#define V_AD_x10000			10834L	/* VAD = 1.0834 */
#define TARGET_VDDx100			330	/* VDD = 3.3 * 10 */
#define VDD_MAX_DIFFx100		20	/* VDD Accur = 0.2*100 */

#define RMS_MULTIPLIERx100		111	/* pi/(2xsqrt(2)) = 1.11*/
#define K_INTDC_RECT_ON			4	/* When Rectifier is ON this value is necessary(2^4) */
#define K_INTDC_RECT_OFF		2	/* 2^2 */
#define RNG_FREQ			25
#define SAMPLING_FREQ			(2000L)
#define N_SAMPLES			(SAMPLING_FREQ/RNG_FREQ)     /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
#define HOOK_THRESH_RING_START_ADDR	0x8B
#define RING_PARAMS_START_ADDR		0x70

#define V_OUT_BATH_MAX_DIFFx100		300	/* 3.0 x100 */
#define V_OUT_BATL_MAX_DIFFx100		400	/* 4.0 x100 */
#define MAX_V_RING_MEANx100		50
#define TARGET_V_RING_RMSx100		2720
#define V_RMS_RING_MAX_DIFFx100		250

#define LM_OK_SRC_IRG_2			(1 << 4)

/************************************************/

#define PORTB		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
#define PORTC		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
#define PORTD		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)

#define _PORTD_SET(mask, state) \
	do { \
		if (state) \
			PORTD |= mask; \
		else \
			PORTD &= ~mask; \
	} while (0)

#define _PORTB_SET(mask, state) \
	do { \
		if (state) \
			PORTB |= mask; \
		else \
			PORTB &= ~mask; \
	} while (0)

#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0)
#define _PORTB_GET(mask) (!!(PORTB & mask))

#define _PORTC_GET(mask) (!!(PORTC & mask))

/* port B */
#define SPI_RXD		(1 << (31 - 28))
#define SPI_TXD		(1 << (31 - 29))
#define SPI_CLK		(1 << (31 - 30))

/* port C */
#define COM_HOOK1	(1 << (15 - 9))
#define COM_HOOK2	(1 << (15 - 10))

#ifndef CONFIG_NETTA_SWAPHOOK

#define COM_HOOK3	(1 << (15 - 11))
#define COM_HOOK4	(1 << (15 - 12))

#else

#define COM_HOOK3	(1 << (15 - 12))
#define COM_HOOK4	(1 << (15 - 11))

#endif

/* port D */
#define SPIENC1		(1 << (15 - 9))
#define SPIENC2		(1 << (15 - 10))
#define SPIENC3		(1 << (15 - 11))
#define SPIENC4		(1 << (15 - 14))

#define SPI_DELAY() udelay(1)

static inline unsigned int __SPI_Transfer(unsigned int tx)
{
	unsigned int rx;
	int b;

	rx = 0; b = 8;
	while (--b >= 0) {
		_PORTB_SET(SPI_TXD, tx & 0x80);
		tx <<= 1;
		_PORTB_TGL(SPI_CLK);
		SPI_DELAY();
		rx <<= 1;
		rx |= _PORTB_GET(SPI_RXD);
		_PORTB_TGL(SPI_CLK);
		SPI_DELAY();
	}

	return rx;
}

static const char *codsp_dtmf_map = "D1234567890*#ABC";

static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 };
static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 };

static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen)
{
	unsigned int rx;
	int i;

	/* just some sanity checks */
	if (cmd == 0 || cmdlen < 0)
		return -1;

	_PORTD_SET(spienc_mask_tab[duslic_id], 0);

	/* first 2 bytes are without response */
	i = 2;
	while (i-- > 0 && cmdlen-- > 0)
		__SPI_Transfer(*cmd++);

	while (cmdlen-- > 0) {
		rx = __SPI_Transfer(*cmd++);
		if (res != 0 && reslen-- > 0)
			*res++ = (unsigned char)rx;
	}
	if (res != 0) {
		while (reslen-- > 0)
			*res++ = __SPI_Transfer(0xFF);
	}

	_PORTD_SET(spienc_mask_tab[duslic_id], 1);

	return 0;
}

/****************************************************************************/

void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m)
{
	unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m);
	codsp_send(duslic_id, &cmd, 1, 0, 0);
}

void codsp_reset_chip(int duslic_id)
{
	static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET;
	codsp_send(duslic_id, &cmd, 1, 0, 0);
}

void codsp_reset_channel(int duslic_id, int channel)
{
	unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH;
	codsp_send(duslic_id, &cmd, 1, 0, 0);
}

void codsp_resync_channel(int duslic_id, int channel)
{
	unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC;
	codsp_send(duslic_id, &cmd, 1, 0, 0);
}

/****************************************************************************/

void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
{
	unsigned char cmd[3];

	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
	cmd[1] = regno;
	cmd[2] = val;

	codsp_send(duslic_id, cmd, 3, 0, 0);
}

void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
{
	unsigned char cmd[4];

	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;