integratorap.c

u-boot-1.1.6 源码包

/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <[e-mail]>
 *
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, <[e-mail]>
 *
 * (C) Copyright 2003
 * Texas Instruments, <www.ti.com>
 * Kshitij Gupta <[e-mail]>
 *
 * (C) Copyright 2004
 * ARM Ltd.
 * Philippe Robin, <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#ifdef CONFIG_PCI
#include <pci.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

void flash__init (void);
void ether__init (void);
void peripheral_power_enable (void);

#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
	printf("Boot reached stage %d\n", progress);
}
#endif

#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)

static inline void delay (unsigned long loops)
{
	__asm__ volatile ("1:\n"
		"subs %0, %1, #1\n"
		"bne 1b":"=r" (loops):"0" (loops));
}

/*
 * Miscellaneous platform dependent initialisations
 */

int board_init (void)
{
	/* arch number of Integrator Board */
	gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = 0x00000100;

	gd->flags = 0;

#ifdef CONFIG_CM_REMAP
extern void cm_remap(void);
	cm_remap();	/* remaps writeable memory to 0x00000000 */
#endif

	icache_enable ();

	flash__init ();
	return 0;
}


int misc_init_r (void)
{
#ifdef CONFIG_PCI
	pci_init();
#endif
	setenv("verify", "n");
	return (0);
}

/*
 * Initialize PCI Devices, report devices found.
 */
#ifdef CONFIG_PCI

#ifndef CONFIG_PCI_PNP

static struct pci_config_table pci_integrator_config_table[] = {
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
				       PCI_ENET0_MEMADDR,
				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
	{ }
};
#endif

/* V3 access routines */
#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
#define _V3Read16(o)	(*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))

#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
#define _V3Read32(o)	(*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))

/* Compute address necessary to access PCI config space for the given */
/* bus and device. */
#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({				\
	unsigned int __address, __devicebit;						\
	unsigned short __mapaddress;							\
	unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */		\
											\
	if (__bus == 0) {								\
		/* local bus segment so need a type 0 config cycle */			\
		/* build the PCI configuration "address" with one-hot in A31-A11 */	\
		__address = PCI_CONFIG_BASE;						\
		__address |= ((__devfn & 0x07) << 8);					\
		__address |= __offset & 0xFF;						\
		__mapaddress = 0x000A;	/* 101=>config cycle, 0=>A1=A0=0 */		\
		__devicebit = (1 << (__dev + 11));					\
											\
		if ((__devicebit & 0xFF000000) != 0) {					\
			/* high order bits are handled by the MAP register */		\
			__mapaddress |= (__devicebit >> 16);				\
		} else {								\
			/* low order bits handled directly in the address */		\
			__address |= __devicebit;					\
		}									\
	} else {		/* bus !=0 */						\
		/* not the local bus segment so need a type 1 config cycle */		\
		/* A31-A24 are don't care (so clear to 0) */				\
		__mapaddress = 0x000B;	/* 101=>config cycle, 1=>A1&A0 from PCI_CFG */	\
		__address = PCI_CONFIG_BASE;						\
		__address |= ((__bus & 0xFF) << 16);	/* bits 23..16 = bus number	*/  \
		__address |= ((__dev & 0x1F) << 11);	/* bits 15..11 = device number	*/  \
		__address |= ((__devfn & 0x07) << 8);	/* bits 10..8  = function number */ \
		__address |= __offset & 0xFF;	/* bits	 7..0  = register number */	\
	}										\
	_V3Write16 (V3_LB_MAP1, __mapaddress);						\
	__address;									\
})

/* _V3OpenConfigWindow - open V3 configuration window */
#define _V3OpenConfigWindow() {								\
	/* Set up base0 to see all 512Mbytes of memory space (not	     */		\
	/* prefetchable), this frees up base1 for re-use by configuration*/		\
	/* memory */									\
											\
	_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |			\
				     0x90 | V3_LB_BASE_M_ENABLE));			\
	/* Set up base1 to point into configuration space, note that MAP1 */		\
	/* register is set up by pciMakeConfigAddress(). */				\
											\
	_V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) |			\
				     0x40 | V3_LB_BASE_M_ENABLE));			\
}

/* _V3CloseConfigWindow - close V3 configuration window */
#define _V3CloseConfigWindow() {							\
    /* Reassign base1 for use by prefetchable PCI memory */				\
	_V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000)	\
					| 0x84 | V3_LB_BASE_M_ENABLE));			\
	_V3Write16 (V3_LB_MAP1,								\
	    (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006);	\
											\
	/* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */	\
											\
	_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |			\
			     0x80 | V3_LB_BASE_M_ENABLE));				\
}

static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev,
				     int offset, unsigned char *val)
{
	_V3OpenConfigWindow ();
	*val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
							       PCI_FUNC (dev),
							       offset);
	_V3CloseConfigWindow ();

	return 0;
}

static int pci_integrator_read__word (struct pci_controller *hose,
				      pci_dev_t dev, int offset,
				      unsigned short *val)
{
	_V3OpenConfigWindow ();
	*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
								PCI_FUNC (dev),
								offset);
	_V3CloseConfigWindow ();

	return 0;
}

static int pci_integrator_read_dword (struct pci_controller *hose,
				      pci_dev_t dev, int offset,
				      unsigned int *val)
{
	_V3OpenConfigWindow ();
	*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
								PCI_FUNC (dev),
								offset);
	*val |= (*(volatile unsigned int *)
		 PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev),
				     (offset + 2))) << 16;
	_V3CloseConfigWindow ();

	return 0;
}

static int pci_integrator_write_byte (struct pci_controller *hose,
				      pci_dev_t dev, int offset,
				      unsigned char val)
{
	_V3OpenConfigWindow ();
	*(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
							PCI_FUNC (dev),
							offset) = val;
	_V3CloseConfigWindow ();

	return 0;
}

static int pci_integrator_write_word (struct pci_controller *hose,
				      pci_dev_t dev, int offset,
				      unsigned short val)
{
	_V3OpenConfigWindow ();
	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
							 PCI_FUNC (dev),
							 offset) = val;
	_V3CloseConfigWindow ();

	return 0;
}

static int pci_integrator_write_dword (struct pci_controller *hose,
				       pci_dev_t dev, int offset,
				       unsigned int val)
{
	_V3OpenConfigWindow ();
	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
							 PCI_FUNC (dev),
							 offset) = (val & 0xFFFF);
	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
							 PCI_FUNC (dev),
							 (offset + 2)) = ((val >> 16) & 0xFFFF);
	_V3CloseConfigWindow ();

	return 0;
}
/******************************
 * PCI initialisation
 ******************************/

struct pci_controller integrator_hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_integrator_config_table,
#endif
};

void pci_init_board (void)
{
	volatile int i, j;
	struct pci_controller *hose = &integrator_hose;

	/* setting this register will take the V3 out of reset */

	*(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1;

	/* wait a few usecs to settle the device and the PCI bus */

	for (i = 0; i < 100; i++)
		j = i + 1;

	/* Now write the Base I/O Address Word to V3_BASE + 0x6C */

	*(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) =
		(unsigned short) (V3_BASE >> 16);

	do {
		*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA;
		*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) =
			0x55;
	} while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA
		 || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA +
						 4) != 0x55);

	/* Make sure that V3 register access is not locked, if it is, unlock it */

	if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &
	     V3_SYSTEM_M_LOCK)
	    == V3_SYSTEM_M_LOCK)
		*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F;

	/* Ensure that the slave accesses from PCI are disabled while we */
	/* setup windows */

	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &=
		~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);

	/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */

	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &=
		~V3_SYSTEM_M_RST_OUT;

	/* Make all accesses from PCI space retry until we're ready for them */