flash.c

u-boot-1.1.6 源码包

			info->size = 0;
			return (0);	/* => no or unknown flash */
		}

	flash_get_offsets ((ulong) addr, info);

	/* Put FLASH back in read mode */
	flash_reset (info);

	return (info->size);
}

#ifdef CFG_FLASH_PROTECTION
/*-----------------------------------------------------------------------
 */

static void flash_sync_real_protect (flash_info_t * info)
{
	FPWV *addr = (FPWV *) (info->start[0]);
	FPWV *sect;
	int i;

	switch (info->flash_id & FLASH_TYPEMASK) {
	case FLASH_28F800C3B:
	case FLASH_28F800C3T:
	case FLASH_28F160C3B:
	case FLASH_28F160C3T:
	case FLASH_28F320C3B:
	case FLASH_28F320C3T:
	case FLASH_28F640C3B:
	case FLASH_28F640C3T:
		/* check for protected sectors */
		*addr = (FPW) 0x00900090;
		for (i = 0; i < info->sector_count; i++) {
			/* read sector protection at sector address, (A7 .. A0) = 0x02.
			 * D0 = 1 for each device if protected.
			 * If at least one device is protected the sector is marked
			 * protected, but mixed protected and  unprotected devices
			 * within a sector should never happen.
			 */
			sect = (FPWV *) (info->start[i]);
			info->protect[i] =
				(sect[2] & (FPW) (0x00010001)) ? 1 : 0;
		}

		/* Put FLASH back in read mode */
		flash_reset (info);
		break;

	case FLASH_AM640U:
	case FLASH_AM800T:
	default:
		/* no hardware protect that we support */
		break;
	}
}
#endif

/*-----------------------------------------------------------------------
 */

int flash_erase (flash_info_t * info, int s_first, int s_last)
{
	FPWV *addr;
	int flag, prot, sect;
	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
	ulong now, last;
	int rcode = 0;

	if ((s_first < 0) || (s_first > s_last)) {
		if (info->flash_id == FLASH_UNKNOWN) {
			printf ("- missing\n");
		} else {
			printf ("- no sectors to erase\n");
		}
		return 1;
	}

	switch (info->flash_id & FLASH_TYPEMASK) {
	case FLASH_INTEL800B:
	case FLASH_INTEL160B:
	case FLASH_INTEL320B:
	case FLASH_INTEL640B:
	case FLASH_28F800C3B:
	case FLASH_28F160C3B:
	case FLASH_28F320C3B:
	case FLASH_28F640C3B:
	case FLASH_AM640U:
	case FLASH_AM800T:
		break;
	case FLASH_UNKNOWN:
	default:
		printf ("Can't erase unknown flash type %08lx - aborted\n",
			info->flash_id);
		return 1;
	}

	prot = 0;
	for (sect = s_first; sect <= s_last; ++sect) {
		if (info->protect[sect]) {
			prot++;
		}
	}

	if (prot) {
		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
	} else {
		printf ("\n");
	}

	reset_timer_masked ();

	/* Start erase on unprotected sectors */
	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {

		if (info->protect[sect] != 0)	/* protected, skip it */
			continue;

		/* Disable interrupts which might cause a timeout here */
		flag = disable_interrupts ();

		reset_timer_masked ();
		last = 0;

		addr = (FPWV *) (info->start[sect]);
		if (intel) {
			*addr = (FPW) 0x00500050;	/* clear status register */
			*addr = (FPW) 0x00200020;	/* erase setup */
			*addr = (FPW) 0x00D000D0;	/* erase confirm */
		} else {
			/* must be AMD style if not Intel */
			FPWV *base;	/* first address in bank */

			base = (FPWV *) (info->start[0]);
			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
			base[0x0555] = (FPW) 0x00800080;	/* erase mode */
			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
			*addr = (FPW) 0x00300030;	/* erase sector */
		}

		/* re-enable interrupts if necessary */
		if (flag)
			enable_interrupts ();

		/* wait at least 50us for AMD, 80us for Intel.
		 * Let's wait 1 ms.
		 */
		udelay (1000);

		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
			if ((now =
			     get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) {
				printf ("Timeout\n");

				if (intel) {
					/* suspend erase        */
					*addr = (FPW) 0x00B000B0;
				}

				flash_reset (info);	/* reset to read mode */
				rcode = 1;	/* failed */
				break;
			}

			/* show that we're waiting */
			if ((now - last) > 1 * CFG_HZ) {	/* every second */
				putc ('.');
				last = now;
			}
		}

		flash_reset (info);	/* reset to read mode   */
	}

	printf (" done\n");
	return rcode;
}

/*-----------------------------------------------------------------------
 * Copy memory to flash, returns:
 * 0 - OK
 * 1 - write timeout
 * 2 - Flash not erased
 */
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
	int bytes;		/* number of bytes to program in current word         */
	int left;		/* number of bytes left to program                    */
	int i, res;

	for (left = cnt, res = 0;
	     left > 0 && res == 0;
	     addr += sizeof (data), left -= sizeof (data) - bytes) {

		bytes = addr & (sizeof (data) - 1);
		addr &= ~(sizeof (data) - 1);

		/* combine source and destination data so can program
		 * an entire word of 16 or 32 bits
		 */
#ifdef CFG_LITTLE_ENDIAN
		for (i = 0; i < sizeof (data); i++) {
			data >>= 8;
			if (i < bytes || i - bytes >= left)
				data += (*((uchar *) addr + i)) << 24;
			else
				data += (*src++) << 24;
		}
#else
		for (i = 0; i < sizeof (data); i++) {
			data <<= 8;
			if (i < bytes || i - bytes >= left)
				data += *((uchar *) addr + i);
			else
				data += *src++;
		}
#endif

		/* write one word to the flash */
		switch (info->flash_id & FLASH_VENDMASK) {
		case FLASH_MAN_AMD:
			res = write_word_amd (info, (FPWV *) addr, data);
			break;
		case FLASH_MAN_INTEL:
			res = write_word_intel (info, (FPWV *) addr, data);
			break;
		default:
			/* unknown flash type, error! */
			printf ("missing or unknown FLASH type\n");
			res = 1;	/* not really a timeout, but gives error */
			break;
		}
	}

	return (res);
}

/*-----------------------------------------------------------------------
 * Write a word to Flash for AMD FLASH
 * A word is 16 or 32 bits, whichever the bus width of the flash bank
 * (not an individual chip) is.
 *
 * returns:
 * 0 - OK
 * 1 - write timeout
 * 2 - Flash not erased
 */
static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
{
	int flag;
	int res = 0;		/* result, assume success       */
	FPWV *base;		/* first address in flash bank  */

	/* Check if Flash is (sufficiently) erased */
	if ((*dest & data) != data) {
		return (2);
	}


	base = (FPWV *) (info->start[0]);

	/* Disable interrupts which might cause a timeout here */
	flag = disable_interrupts ();

	base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
	base[0x02AA] = (FPW) 0x00550055;	/* unlock */
	base[0x0555] = (FPW) 0x00A000A0;	/* selects program mode */

	*dest = data;		/* start programming the data   */

	/* re-enable interrupts if necessary */
	if (flag)
		enable_interrupts ();

	reset_timer_masked ();

	/* data polling for D7 */
	while (res == 0
	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
			*dest = (FPW) 0x00F000F0;	/* reset bank */
			res = 1;
		}
	}

	return (res);
}

/*-----------------------------------------------------------------------
 * Write a word to Flash for Intel FLASH
 * A word is 16 or 32 bits, whichever the bus width of the flash bank
 * (not an individual chip) is.
 *
 * returns:
 * 0 - OK
 * 1 - write timeout
 * 2 - Flash not erased
 */
static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data)
{
	int flag;
	int res = 0;		/* result, assume success       */

	/* Check if Flash is (sufficiently) erased */
	if ((*dest & data) != data) {
		return (2);
	}

	/* Disable interrupts which might cause a timeout here */
	flag = disable_interrupts ();

	*dest = (FPW) 0x00500050;	/* clear status register        */
	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
	*dest = (FPW) 0x00400040;	/* program setup                */

	*dest = data;		/* start programming the data   */

	/* re-enable interrupts if necessary */
	if (flag)
		enable_interrupts ();

	reset_timer_masked ();

	while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
			*dest = (FPW) 0x00B000B0;	/* Suspend program      */
			res = 1;
		}
	}

	if (res == 0 && (*dest & (FPW) 0x00100010))
		res = 1;	/* write failed, time out error is close enough */

	*dest = (FPW) 0x00500050;	/* clear status register        */
	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */

	return (res);
}

#ifdef CFG_FLASH_PROTECTION
/*-----------------------------------------------------------------------
 */
int flash_real_protect (flash_info_t * info, long sector, int prot)
{
	int rcode = 0;		/* assume success */
	FPWV *addr;		/* address of sector */
	FPW value;

	addr = (FPWV *) (info->start[sector]);

	switch (info->flash_id & FLASH_TYPEMASK) {
	case FLASH_28F800C3B:
	case FLASH_28F800C3T:
	case FLASH_28F160C3B:
	case FLASH_28F160C3T:
	case FLASH_28F320C3B:
	case FLASH_28F320C3T:
	case FLASH_28F640C3B:
	case FLASH_28F640C3T:
		flash_reset (info);	/* make sure in read mode */
		*addr = (FPW) 0x00600060L;	/* lock command setup */
		if (prot)
			*addr = (FPW) 0x00010001L;	/* lock sector */
		else
			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
		flash_reset (info);	/* reset to read mode */

		/* now see if it really is locked/unlocked as requested */
		*addr = (FPW) 0x00900090;
		/* read sector protection at sector address, (A7 .. A0) = 0x02.
		 * D0 = 1 for each device if protected.
		 * If at least one device is protected the sector is marked
		 * protected, but return failure. Mixed protected and
		 * unprotected devices within a sector should never happen.
		 */
		value = addr[2] & (FPW) 0x00010001;
		if (value == 0)
			info->protect[sector] = 0;
		else if (value == (FPW) 0x00010001)
			info->protect[sector] = 1;
		else {
			/* error, mixed protected and unprotected */
			rcode = 1;
			info->protect[sector] = 1;
		}
		if (info->protect[sector] != prot)
			rcode = 1;	/* failed to protect/unprotect as requested */

		/* reload all protection bits from hardware for now */
		flash_sync_real_protect (info);
		break;

	case FLASH_AM640U:
	case FLASH_AM800T:
	default:
		/* no hardware protect that we support */
		info->protect[sector] = prot;
		break;
	}

	return rcode;
}
#endif