speed.c

u-boot-1.1.6 源码包

#endif

#if defined(CONFIG_440SPE)
unsigned long determine_sysper(void)
{
	unsigned int fpga_clocking_reg;
	unsigned int master_clock_selection;
	unsigned long master_clock_per = 0;
	unsigned long fb_div_selection;
	unsigned int vco_div_reg_value;
	unsigned long vco_div_selection;
	unsigned long sys_per = 0;
	int extClkVal;

	/*-------------------------------------------------------------------------+
	 | Read FPGA reg 0 and reg 1 to get FPGA reg information
	 +-------------------------------------------------------------------------*/
	fpga_clocking_reg = in16(FPGA_REG16);


	/* Determine Master Clock Source Selection */
	master_clock_selection = fpga_clocking_reg & FPGA_REG16_MASTER_CLK_MASK;

	switch(master_clock_selection) {
		case FPGA_REG16_MASTER_CLK_66_66:
			master_clock_per = PERIOD_66_66MHZ;
			break;
		case FPGA_REG16_MASTER_CLK_50:
			master_clock_per = PERIOD_50_00MHZ;
			break;
		case FPGA_REG16_MASTER_CLK_33_33:
			master_clock_per = PERIOD_33_33MHZ;
			break;
		case FPGA_REG16_MASTER_CLK_25:
			master_clock_per = PERIOD_25_00MHZ;
			break;
		case FPGA_REG16_MASTER_CLK_EXT:
			if ((extClkVal==EXTCLK_33_33)
					&& (extClkVal==EXTCLK_50)
					&& (extClkVal==EXTCLK_66_66)
					&& (extClkVal==EXTCLK_83)) {
				/* calculate master clock period from external clock value */
				master_clock_per=(ONE_BILLION/extClkVal) * 1000;
			} else {
				/* Unsupported */
				DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
				hang();
			}
			break;
		default:
			/* Unsupported */
			DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
			hang();
			break;
	}

	/* Determine FB divisors values */
	if ((fpga_clocking_reg & FPGA_REG16_FB1_DIV_MASK) == FPGA_REG16_FB1_DIV_LOW) {
		if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
			fb_div_selection = FPGA_FB_DIV_6;
		else
			fb_div_selection = FPGA_FB_DIV_12;
	} else {
		if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
			fb_div_selection = FPGA_FB_DIV_10;
		else
			fb_div_selection = FPGA_FB_DIV_20;
	}

	/* Determine VCO divisors values */
	vco_div_reg_value = fpga_clocking_reg & FPGA_REG16_VCO_DIV_MASK;

	switch(vco_div_reg_value) {
		case FPGA_REG16_VCO_DIV_4:
			vco_div_selection = FPGA_VCO_DIV_4;
			break;
		case FPGA_REG16_VCO_DIV_6:
			vco_div_selection = FPGA_VCO_DIV_6;
			break;
		case FPGA_REG16_VCO_DIV_8:
			vco_div_selection = FPGA_VCO_DIV_8;
			break;
		case FPGA_REG16_VCO_DIV_10:
		default:
			vco_div_selection = FPGA_VCO_DIV_10;
			break;
	}

	if (master_clock_selection == FPGA_REG16_MASTER_CLK_EXT) {
		switch(master_clock_per) {
			case PERIOD_25_00MHZ:
				if (fb_div_selection == FPGA_FB_DIV_12) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_75_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_50_00MHZ;
				}
				break;
			case PERIOD_33_33MHZ:
				if (fb_div_selection == FPGA_FB_DIV_6) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_50_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_33_33MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_10) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_83_33MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_10)
						sys_per = PERIOD_33_33MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_12) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_100_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_66_66MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_8)
						sys_per = PERIOD_50_00MHZ;
				}
				break;
			case PERIOD_50_00MHZ:
				if (fb_div_selection == FPGA_FB_DIV_6) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_75_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_50_00MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_10) {
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_83_33MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_10)
						sys_per = PERIOD_50_00MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_12) {
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_100_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_8)
						sys_per = PERIOD_75_00MHZ;
				}
				break;
			case PERIOD_66_66MHZ:
				if (fb_div_selection == FPGA_FB_DIV_6) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_100_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_66_66MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_8)
						sys_per = PERIOD_50_00MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_10) {
					if (vco_div_selection == FPGA_VCO_DIV_8)
						sys_per = PERIOD_83_33MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_10)
						sys_per = PERIOD_66_66MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_12) {
					if (vco_div_selection == FPGA_VCO_DIV_8)
						sys_per = PERIOD_100_00MHZ;
				}
				break;
			default:
				break;
		}

		if (sys_per == 0) {
			/* Other combinations are not supported */
			DEBUGF ("%s[%d] *** sys period compute failed ***\n", __FUNCTION__,__LINE__);
			hang();
		}
	} else {
		/* calcul system clock without cheking */
		/* if engineering option clock no check is selected */
		/* sys_per = master_clock_per * vco_div_selection / fb_div_selection */
		sys_per = (master_clock_per/fb_div_selection) * vco_div_selection;
	}

	return(sys_per);

}

/*-------------------------------------------------------------------------+
| determine_pci_clock_per.
+-------------------------------------------------------------------------*/
unsigned long determine_pci_clock_per(void)
{
	unsigned long pci_clock_selection,  pci_period;

	/*-------------------------------------------------------------------------+
	 | Read FPGA reg 6 to get PCI 0 FPGA reg information
	 +-------------------------------------------------------------------------*/
	pci_clock_selection = in16(FPGA_REG16);	/* was reg6 averifier */


	pci_clock_selection = pci_clock_selection & FPGA_REG16_PCI0_CLK_MASK;

	switch (pci_clock_selection) {
		case FPGA_REG16_PCI0_CLK_133_33:
			pci_period = PERIOD_133_33MHZ;
			break;
		case FPGA_REG16_PCI0_CLK_100:
			pci_period = PERIOD_100_00MHZ;
			break;
		case FPGA_REG16_PCI0_CLK_66_66:
			pci_period = PERIOD_66_66MHZ;
			break;
		default:
			pci_period = PERIOD_33_33MHZ;;
			break;
	}

	return(pci_period);
}
#endif

ulong get_OPB_freq (void)
{

	sys_info_t sys_info;
	get_sys_info (&sys_info);
	return sys_info.freqOPB;
}

#elif defined(CONFIG_XILINX_ML300)
extern void get_sys_info (sys_info_t * sysInfo);
extern ulong get_PCI_freq (void);

#elif defined(CONFIG_AP1000)
void get_sys_info (sys_info_t * sysInfo) {
	sysInfo->freqProcessor = 240 * 1000 * 1000;
	sysInfo->freqPLB = 80 * 1000 * 1000;
	sysInfo->freqPCI = 33 * 1000 * 1000;
}

#elif defined(CONFIG_405)

void get_sys_info (sys_info_t * sysInfo) {

	sysInfo->freqVCOMhz=3125000;
	sysInfo->freqProcessor=12*1000*1000;
	sysInfo->freqPLB=50*1000*1000;
	sysInfo->freqPCI=66*1000*1000;

}

#elif defined(CONFIG_405EP)
void get_sys_info (PPC405_SYS_INFO * sysInfo)
{
	unsigned long pllmr0;
	unsigned long pllmr1;
	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
	unsigned long m;
	unsigned long pllmr0_ccdv;

	/*
	 * Read PLL Mode registers
	 */
	pllmr0 = mfdcr (cpc0_pllmr0);
	pllmr1 = mfdcr (cpc0_pllmr1);

	/*
	 * Determine forward divider A
	 */
	sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16);

	/*
	 * Determine forward divider B (should be equal to A)
	 */
	sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12);

	/*
	 * Determine FBK_DIV.
	 */
	sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
	if (sysInfo->pllFbkDiv == 0) {
		sysInfo->pllFbkDiv = 16;
	}

	/*
	 * Determine PLB_DIV.
	 */
	sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;

	/*
	 * Determine PCI_DIV.
	 */
	sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1;

	/*
	 * Determine EXTBUS_DIV.
	 */
	sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2;

	/*
	 * Determine OPB_DIV.
	 */
	sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1;

	/*
	 * Determine the M factor
	 */
	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;

	/*
	 * Determine VCO clock frequency
	 */
	sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
		(unsigned long long)sysClkPeriodPs;

	/*
	 * Determine CPU clock frequency
	 */
	pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
	if (pllmr1 & PLLMR1_SSCS_MASK) {
		/*
		 * This is true if FWDVA == FWDVB:
		 * sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
		 *	/ pllmr0_ccdv;
		 */
		sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB)
			/ sysInfo->pllFwdDiv / pllmr0_ccdv;
	} else {
		sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
	}

	/*
	 * Determine PLB clock frequency
	 */
	sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
}


/********************************************
 * get_OPB_freq
 * return OPB bus freq in Hz
 *********************************************/
ulong get_OPB_freq (void)
{
	ulong val = 0;

	PPC405_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllOpbDiv;

	return val;
}


/********************************************
 * get_PCI_freq
 * return PCI bus freq in Hz
 *********************************************/
ulong get_PCI_freq (void)
{
	ulong val;
	PPC405_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllPciDiv;
	return val;
}

#endif

int get_clocks (void)
{
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
	sys_info_t sys_info;

	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freqProcessor;
	gd->bus_clk = sys_info.freqPLB;

#endif	/* defined(CONFIG_405GP) || defined(CONFIG_405CR) */

#ifdef CONFIG_IOP480
	gd->cpu_clk = 66000000;
	gd->bus_clk = 66000000;
#endif
	return (0);
}


/********************************************
 * get_bus_freq
 * return PLB bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	ulong val;

#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
	sys_info_t sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB;

#elif defined(CONFIG_IOP480)

	val = 66;

#else
# error get_bus_freq() not implemented
#endif

	return val;
}