immap_83xx.h

u-boot-1.1.6 源码包

#define CSCONFIG_COL_BIT    0x00000007
#define CSCONFIG_COL_BIT_8  0x00000000
#define CSCONFIG_COL_BIT_9  0x00000001
#define CSCONFIG_COL_BIT_10 0x00000002
#define CSCONFIG_COL_BIT_11 0x00000003
	u8 res1[0x78];
	u32 timing_cfg_1;       /**< SDRAM Timing Configuration 1 */
#define TIMING_CFG1_PRETOACT 0x70000000
#define TIMING_CFG1_PRETOACT_SHIFT   28
#define TIMING_CFG1_ACTTOPRE 0x0F000000
#define TIMING_CFG1_ACTTOPRE_SHIFT   24
#define TIMING_CFG1_ACTTORW  0x00700000
#define TIMING_CFG1_ACTTORW_SHIFT    20
#define TIMING_CFG1_CASLAT   0x00070000
#define TIMING_CFG1_CASLAT_SHIFT     16
#define TIMING_CFG1_REFREC   0x0000F000
#define TIMING_CFG1_REFREC_SHIFT     12
#define TIMING_CFG1_WRREC    0x00000700
#define TIMING_CFG1_WRREC_SHIFT       8
#define TIMING_CFG1_ACTTOACT 0x00000070
#define TIMING_CFG1_ACTTOACT_SHIFT    4
#define TIMING_CFG1_WRTORD   0x00000007
#define TIMING_CFG1_WRTORD_SHIFT      0
#define TIMING_CFG1_CASLAT_20 0x00030000  /* CAS latency = 2.0 */
#define TIMING_CFG1_CASLAT_25 0x00040000  /* CAS latency = 2.5 */

	u32 timing_cfg_2;       /**< SDRAM Timing Configuration 2 */
#define TIMING_CFG2_CPO           0x0F000000
#define TIMING_CFG2_CPO_SHIFT             24
#define TIMING_CFG2_ACSM          0x00080000
#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT   10
#define TIMING_CFG2_CPO_DEF       0x00000000  /* default (= CASLAT + 1) */

	u32 sdram_cfg;          /**< SDRAM Control Configuration */
#define SDRAM_CFG_MEM_EN     0x80000000
#define SDRAM_CFG_SREN       0x40000000
#define SDRAM_CFG_ECC_EN     0x20000000
#define SDRAM_CFG_RD_EN      0x10000000
#define SDRAM_CFG_SDRAM_TYPE 0x03000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT   24
#define SDRAM_CFG_DYN_PWR    0x00200000
#define SDRAM_CFG_32_BE      0x00080000
#define SDRAM_CFG_8_BE       0x00040000
#define SDRAM_CFG_NCAP       0x00020000
#define SDRAM_CFG_2T_EN      0x00008000
#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000

	u8 res2[4];
	u32 sdram_mode;         /**< SDRAM Mode Configuration */
#define SDRAM_MODE_ESD 0xFFFF0000
#define SDRAM_MODE_ESD_SHIFT   16
#define SDRAM_MODE_SD  0x0000FFFF
#define SDRAM_MODE_SD_SHIFT     0
#define DDR_MODE_EXT_MODEREG    0x4000  /* select extended mode reg */
#define DDR_MODE_EXT_OPMODE     0x3FF8  /* operating mode, mask */
#define DDR_MODE_EXT_OP_NORMAL  0x0000  /* normal operation */
#define DDR_MODE_QFC            0x0004  /* QFC / compatibility, mask */
#define DDR_MODE_QFC_COMP       0x0000  /* compatible to older SDRAMs */
#define DDR_MODE_WEAK           0x0002  /* weak drivers */
#define DDR_MODE_DLL_DIS        0x0001  /* disable DLL */
#define DDR_MODE_CASLAT         0x0070  /* CAS latency, mask */
#define DDR_MODE_CASLAT_15      0x0010  /* CAS latency 1.5 */
#define DDR_MODE_CASLAT_20      0x0020  /* CAS latency 2 */
#define DDR_MODE_CASLAT_25      0x0060  /* CAS latency 2.5 */
#define DDR_MODE_CASLAT_30      0x0030  /* CAS latency 3 */
#define DDR_MODE_BTYPE_SEQ      0x0000  /* sequential burst */
#define DDR_MODE_BTYPE_ILVD     0x0008  /* interleaved burst */
#define DDR_MODE_BLEN_2         0x0001  /* burst length 2 */
#define DDR_MODE_BLEN_4         0x0002  /* burst length 4 */
#define DDR_REFINT_166MHZ_7US   1302        /* exact value for 7.8125 µs */
#define DDR_BSTOPRE     256     /* use 256 cycles as a starting point */
#define DDR_MODE_MODEREG        0x0000  /* select mode register */

	u8 res3[8];
	u32 sdram_interval;     /**< SDRAM Interval Configuration */
#define SDRAM_INTERVAL_REFINT  0x3FFF0000
#define SDRAM_INTERVAL_REFINT_SHIFT    16
#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
#define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
	u8   res9[8];
	u32  sdram_clk_cntl;
#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025	0x01000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075	0x03000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1		0x04000000

	u8 res4[0xCCC];
	u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
	u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
	u32 ecc_err_inject;     /**< Memory Data Path Error Injection Mask ECC */
#define ECC_ERR_INJECT_EMB			(0x80000000>>22)	/* ECC Mirror Byte */
#define ECC_ERR_INJECT_EIEN			(0x80000000>>23)	/* Error Injection Enable */
#define ECC_ERR_INJECT_EEIM			(0xff000000>>24)	/* ECC Erroe Injection Enable */
#define ECC_ERR_INJECT_EEIM_SHIFT		0
	u8 res5[0x14];
	u32 capture_data_hi;    /**< Memory Data Path Read Capture High */
	u32 capture_data_lo;    /**< Memory Data Path Read Capture Low */
	u32 capture_ecc;        /**< Memory Data Path Read Capture ECC */
#define CAPTURE_ECC_ECE				(0xff000000>>24)
#define CAPTURE_ECC_ECE_SHIFT			0
	u8 res6[0x14];
	u32 err_detect;         /**< Memory Error Detect */
#define ECC_ERROR_DETECT_MME			(0x80000000>>0)		/* Multiple Memory Errors */
#define ECC_ERROR_DETECT_MBE			(0x80000000>>28)	/* Multiple-Bit Error */
#define ECC_ERROR_DETECT_SBE			(0x80000000>>29)	/* Single-Bit ECC Error Pickup */
#define ECC_ERROR_DETECT_MSE			(0x80000000>>31)	/* Memory Select Error */
	u32 err_disable;        /**< Memory Error Disable */
#define ECC_ERROR_DISABLE_MBED			(0x80000000>>28)	/* Multiple-Bit ECC Error Disable */
#define ECC_ERROR_DISABLE_SBED			(0x80000000>>29)	/* Sinle-Bit ECC Error disable */
#define ECC_ERROR_DISABLE_MSED			(0x80000000>>31)	/* Memory Select Error Disable */
#define ECC_ERROR_ENABLE			~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED)
	u32 err_int_en;         /**< Memory Error Interrupt Enable */
#define ECC_ERR_INT_EN_MBEE			(0x80000000>>28)	/* Multiple-Bit ECC Error Interrupt Enable */
#define ECC_ERR_INT_EN_SBEE			(0x80000000>>29)	/* Single-Bit ECC Error Interrupt Enable */
#define ECC_ERR_INT_EN_MSEE			(0x80000000>>31)	/* Memory Select Error Interrupt Enable */
#define ECC_ERR_INT_DISABLE			~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE)
	u32 capture_attributes; /**< Memory Error Attributes Capture */
#define ECC_CAPT_ATTR_BNUM			(0xe0000000>>1)		/* Data Beat Num */
#define ECC_CAPT_ATTR_BNUM_SHIFT		28
#define ECC_CAPT_ATTR_TSIZ			(0xc0000000>>6)		/* Transaction Size */
#define ECC_CAPT_ATTR_TSIZ_FOUR_DW		0
#define ECC_CAPT_ATTR_TSIZ_ONE_DW		1
#define ECC_CAPT_ATTR_TSIZ_TWO_DW		2
#define ECC_CAPT_ATTR_TSIZ_THREE_DW		3
#define ECC_CAPT_ATTR_TSIZ_SHIFT		24
#define ECC_CAPT_ATTR_TSRC			(0xf8000000>>11)	/* Transaction Source */
#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT		0x0
#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF		0x2
#define ECC_CAPT_ATTR_TSRC_TSEC1		0x4
#define ECC_CAPT_ATTR_TSRC_TSEC2		0x5
#define ECC_CAPT_ATTR_TSRC_USB			(0x06|0x07)
#define ECC_CAPT_ATTR_TSRC_ENCRYPT		0x8
#define ECC_CAPT_ATTR_TSRC_I2C			0x9
#define ECC_CAPT_ATTR_TSRC_JTAG			0xA
#define ECC_CAPT_ATTR_TSRC_PCI1			0xD
#define ECC_CAPT_ATTR_TSRC_PCI2			0xE
#define ECC_CAPT_ATTR_TSRC_DMA			0xF
#define ECC_CAPT_ATTR_TSRC_SHIFT		16
#define ECC_CAPT_ATTR_TTYP			(0xe0000000>>18)	/* Transaction Type */
#define ECC_CAPT_ATTR_TTYP_WRITE		0x1
#define ECC_CAPT_ATTR_TTYP_READ			0x2
#define ECC_CAPT_ATTR_TTYP_R_M_W		0x3
#define ECC_CAPT_ATTR_TTYP_SHIFT		12
#define ECC_CAPT_ATTR_VLD			(0x80000000>>31)	/* Valid */
	u32 capture_address;    /**< Memory Error Address Capture */
	u32 capture_ext_address;/**< Memory Error Extended Address Capture */
	u32 err_sbe;            /**< Memory Single-Bit ECC Error Management */
#define ECC_ERROR_MAN_SBET			(0xff000000>>8)		/* Single-Bit Error Threshold 0..255*/
#define ECC_ERROR_MAN_SBET_SHIFT		16
#define ECC_ERROR_MAN_SBEC			(0xff000000>>24)	/* Single Bit Error Counter 0..255*/
#define ECC_ERROR_MAN_SBEC_SHIFT		0
	u8 res7[0xA4];
	u32 debug_reg;
	u8 res8[0xFC];
} ddr8349_t;

/*
 * I2C1 Controller
 */


/*
 * DUART
 */
typedef struct duart8349{
	u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
	u8 uier_udmb;      /**< combined register for UIER and UDMB */
	u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
	u8 ulcr;        /**< line control register */
	u8 umcr;        /**< MODEM control register */
	u8 ulsr;        /**< line status register */
	u8 umsr;        /**< MODEM status register */
	u8 uscr;        /**< scratch register */
	u8 res0[8];
	u8 udsr;        /**< DMA status register */
	u8 res1[3];
	u8 res2[0xEC];
} duart8349_t;

/*
 * Local Bus Controller Registers
 */
typedef struct lbus_bank{
	u32 br;             /**< Base Register  */
	u32 or;             /**< Base Register  */
} lbus_bank_t;

typedef struct lbus8349 {
	lbus_bank_t bank[8];
	u8 res0[0x28];
	u32 mar;                /**< UPM Address Register */
	u8 res1[0x4];
	u32 mamr;               /**< UPMA Mode Register */
	u32 mbmr;               /**< UPMB Mode Register */
	u32 mcmr;               /**< UPMC Mode Register */
	u8 res2[0x8];
	u32 mrtpr;              /**< Memory Refresh Timer Prescaler Register */
	u32 mdr;                /**< UPM Data Register */
	u8 res3[0x8];
	u32 lsdmr;              /**< SDRAM Mode Register */
	u8 res4[0x8];
	u32 lurt;               /**< UPM Refresh Timer */
	u32 lsrt;               /**< SDRAM Refresh Timer */
	u8 res5[0x8];
	u32 ltesr;              /**< Transfer Error Status Register */
	u32 ltedr;              /**< Transfer Error Disable Register */
	u32 lteir;              /**< Transfer Error Interrupt Register */
	u32 lteatr;             /**< Transfer Error Attributes Register */
	u32 ltear;              /**< Transfer Error Address Register */
	u8 res6[0xC];
	u32 lbcr;               /**< Configuration Register */
#define LBCR_LDIS  0x80000000
#define LBCR_LDIS_SHIFT    31
#define LBCR_BCTLC 0x00C00000
#define LBCR_BCTLC_SHIFT   22
#define LBCR_LPBSE 0x00020000
#define LBCR_LPBSE_SHIFT   17
#define LBCR_EPAR  0x00010000
#define LBCR_EPAR_SHIFT    16
#define LBCR_BMT   0x0000FF00
#define LBCR_BMT_SHIFT      8
	u32 lcrr;               /**< Clock Ratio Register */
#define LCRR_DBYP    0x80000000
#define LCRR_DBYP_SHIFT      31
#define LCRR_BUFCMDC 0x30000000
#define LCRR_BUFCMDC_SHIFT   28
#define LCRR_ECL     0x03000000
#define LCRR_ECL_SHIFT       24
#define LCRR_EADC    0x00030000
#define LCRR_EADC_SHIFT      16
#define LCRR_CLKDIV  0x0000000F
#define LCRR_CLKDIV_SHIFT     0


	u8 res7[0x28];
	u8 res8[0xF00];
} lbus8349_t;

/*
 * Serial Peripheral Interface
 */
typedef struct spi8349
{
	u32 mode;     /**< mode register  */
	u32 event;    /**< event register */
	u32 mask;     /**< mask register  */
	u32 com;      /**< command register */
	u8 res0[0x10];
	u32 tx;       /**< transmit register */
	u32 rx;       /**< receive register */
	u8 res1[0xD8];
} spi8349_t;


/*
 * DMA/Messaging Unit
 */
typedef struct dma8349 {
	u32 res0[0xC];	/* 0x0-0x29 reseverd */
	u32 omisr;	/* 0x30 Outbound message interrupt status register */
	u32 omimr;	/* 0x34 Outbound message interrupt mask register */
	u32 res1[0x6];	/* 0x38-0x49 reserved */

	u32 imr0;	/* 0x50 Inbound message register 0 */
	u32 imr1;	/* 0x54 Inbound message register 1 */
	u32 omr0;	/* 0x58 Outbound message register 0 */
	u32 omr1;	/* 0x5C Outbound message register 1 */

	u32 odr;	/* 0x60 Outbound doorbell register */
	u32 res2;	/* 0x64-0x67 reserved */
	u32 idr;	/* 0x68 Inbound doorbell register */
	u32 res3[0x5];	/* 0x6C-0x79 reserved */

	u32 imisr;	/* 0x80 Inbound message interrupt status register */
	u32 imimr;	/* 0x84 Inbound message interrupt mask register */
	u32 res4[0x1E];	/* 0x88-0x99 reserved */

	u32 dmamr0;	/* 0x100 DMA 0 mode register */
	u32 dmasr0;	/* 0x104 DMA 0 status register */
	u32 dmacdar0;	/* 0x108 DMA 0 current descriptor address register */
	u32 res5;	/* 0x10C reserved */
	u32 dmasar0;	/* 0x110 DMA 0 source address register */
	u32 res6;	/* 0x114 reserved */
	u32 dmadar0;	/* 0x118 DMA 0 destination address register */
	u32 res7;	/* 0x11C reserved */
	u32 dmabcr0;	/* 0x120 DMA 0 byte count register */
	u32 dmandar0;	/* 0x124 DMA 0 next descriptor address register */
	u32 res8[0x16];	/* 0x128-0x179 reserved */

	u32 dmamr1;	/* 0x180 DMA 1 mode register */
	u32 dmasr1;	/* 0x184 DMA 1 status register */
	u32 dmacdar1;	/* 0x188 DMA 1 current descriptor address register */
	u32 res9;	/* 0x18C reserved */
	u32 dmasar1;	/* 0x190 DMA 1 source address register */
	u32 res10;	/* 0x194 reserved */