immap_86xx.h

u-boot-1.1.6 源码包

	uint	pgccsr;		/* 0xc013c - Port General Command and Status Register */
	uint	plmreqcsr;	/* 0xc0140 - Port Link Maintenance Request Command and Status Register */
	uint	plmrespcsr;	/* 0xc0144 - Port Link Maintenance Response Command and Status Register */
	uint	plascsr;	/* 0xc0148 - Port Local Ackid Status Command and Status Register */
	char	res8[12];
	uint	pescsr;		/* 0xc0158 - Port Error and Status Command and Status Register */
	uint	pccsr;		/* 0xc015c - Port Control Command and Status Register */
	char	res9[1184];
	uint	erbh;		/* 0xc0600 - Error Reporting Block Header Register */
	char	res10[4];
	uint	ltledcsr;	/* 0xc0608 - Logical/Transport layer error detect status register */
	uint	ltleecsr;	/* 0xc060c - Logical/Transport layer error enable register */
	char	res11[4];
	uint	ltlaccsr;	/* 0xc0614 - Logical/Transport layer addresss capture register */
	uint	ltldidccsr;	/* 0xc0618 - Logical/Transport layer device ID capture register */
	uint	ltlcccsr;	/* 0xc061c - Logical/Transport layer control capture register */
	char	res12[32];
	uint	edcsr;	        /* 0xc0640 - Port 0 error detect status register */
	uint	erecsr;	        /* 0xc0644 - Port 0 error rate enable status register */
	uint	ecacsr;	        /* 0xc0648 - Port 0 error capture attributes register */
	uint	pcseccsr0;	/* 0xc064c - Port 0 packet/control symbol error capture register 0 */
	uint	peccsr1;	/* 0xc0650 - Port 0 error capture command and status register 1 */
	uint	peccsr2;	/* 0xc0654 - Port 0 error capture command and status register 2 */
	uint	peccsr3;	/* 0xc0658 - Port 0 error capture command and status register 3 */
	char	res13[12];
	uint	ercsr;	        /* 0xc0668 - Port 0 error rate command and status register */
	uint	ertcsr;	        /* 0xc066C - Port 0 error rate threshold status register*/
	char	res14[63892];
	uint	llcr;		/* 0xd0004 - Logical Layer Configuration Register */
	char	res15[12];
	uint	epwisr;		/* 0xd0010 - Error / Port-Write Interrupt Status Register */
	char	res16[12];
	uint	lretcr;		/* 0xd0020 - Logical Retry Error Threshold Configuration Register */
	char	res17[92];
	uint	pretcr;		/* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
	char	res18[124];
	uint	adidcsr;	/* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
	char	res19[28];
	uint	ptaacr;	        /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
	char	res20[12];
	uint	iecsr;	        /* 0xd0130 - Port 0 Implementation Error Status Register */
	char	res21[12];
	uint	pcr;		/* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
	char	res22[20];
	uint	slcsr;	        /* 0xd0158 - Port 0 Serial Link Command and Status Register */
	char	res23[4];
	uint	sleir;	        /* 0xd0160 - Port 0 Serial Link Error Injection Register */
	char	res24[2716];
	uint	rowtar0;	/* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
	uint	rowtear0;	/* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
	char	res25[8];
	uint	rowar0;		/* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
	char	res26[12];
	uint	rowtar1;	/* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
	uint	rowtear1;	/* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
	uint	rowbar1;	/* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
	char	res27[4];
	uint	rowar1;		/* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
	uint	rows1r1;	/* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
	uint	rows2r1;	/* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
	uint	rows3r1;	/* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
	uint	rowtar2;	/* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
	uint	rowtear2;	/* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
	uint	rowbar2;	/* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
	char	res28[4];
	uint	rowar2;		/* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
	uint	rows1r2;	/* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
	uint	rows2r2;	/* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
	uint	rows3r2;	/* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
	uint	rowtar3;	/* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
	uint	rowtear3;	/* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
	uint	rowbar3;	/* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
	char	res29[4];
	uint	rowar3;		/* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
	uint	rows1r3;	/* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
	uint	rows2r3;	/* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
	uint	rows3r3;	/* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
	uint	rowtar4;	/* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
	uint	rowtear4;	/* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
	uint	rowbar4;	/* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
	char	res30[4];
	uint	rowar4;		/* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
	uint	rows1r4;	/* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
	uint	rows2r4;	/* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
	uint	rows3r4;	/* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
	uint	rowtar5;	/* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
	uint	rowtear5;	/* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
	uint	rowbar5;	/* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
	char	res31[4];
	uint	rowar5;		/* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
	uint	rows1r5;	/* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
	uint	rows2r5;	/* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
	uint	rows3r5;	/* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
	uint	rowtar6;	/* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
	uint	rowtear6;	/* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
	uint	rowbar6;	/* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
	char	res32[4];
	uint	rowar6;		/* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
	uint	rows1r6;	/* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
	uint	rows2r6;	/* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
	uint	rows3r6;	/* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
	uint	rowtar7;	/* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
	uint	rowtear7;	/* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
	uint	rowbar7;	/* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
	char	res33[4];
	uint	rowar7;		/* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
	uint	rows1r7;	/* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
	uint	rows2r7;	/* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
	uint	rows3r7;	/* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
	uint	rowtar8;	/* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
	uint	rowtear8;	/* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
	uint	rowbar8;	/* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
	char	res34[4];
	uint	rowar8;		/* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
	uint	rows1r8;	/* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
	uint	rows2r8;	/* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
	uint	rows3r8;	/* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
	char	res35[64];
	uint	riwtar4;	/* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
	uint	riwbar4;	/* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
	char	res36[4];
	uint	riwar4;		/* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
	char	res37[12];
	uint	riwtar3;	/* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
	char	res38[4];
	uint	riwbar3;	/* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
	char	res39[4];
	uint	riwar3;		/* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
	char	res40[12];
	uint	riwtar2;	/* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
	char	res41[4];
	uint	riwbar2;	/* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
	char	res42[4];
	uint	riwar2;		/* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
	char	res43[12];
	uint	riwtar1;	/* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
	char	res44[4];
	uint	riwbar1;	/* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
	char	res45[4];
	uint	riwar1;		/* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
	char	res46[12];
	uint	riwtar0;	/* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
	char	res47[12];
	uint	riwar0;		/* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
	char	res48[12];
	uint	pnfedr;		/* 0xd0e00 - Port Notification/Fatal Error Detect Register */
	uint	pnfedir;	/* 0xd0e04 - Port Notification/Fatal Error Detect Register */
	uint	pnfeier;	/* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
	uint	pecr;		/* 0xd0e0c - Port Error Control Register */
	uint	pepcsr0;	/* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
	uint	pepr1;		/* 0xd0e14 - Port Error Packet Register 1 */
	uint	pepr2;		/* 0xd0e18 - Port Error Packet Register 2 */
	char	res49[4];
	uint	predr;		/* 0xd0e20 - Port Recoverable Error Detect Register */
	char	res50[4];
	uint	pertr;		/* 0xd0e28 - Port Error Recovery Threshold Register */
	uint	prtr;		/* 0xd0e2c - Port Retry Threshold Register */
	char	res51[8656];
	uint	omr;		/* 0xd3000 - Outbound Mode Register */
	uint	osr;		/* 0xd3004 - Outbound Status Register */
	uint	eodqtpar;	/* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
	uint	odqtpar;	/* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
	uint	eosar;		/* 0xd3010 - Extended Outbound Unit Source Address Register */
	uint	osar;		/* 0xd3014 - Outbound Unit Source Address Register */
	uint	odpr;		/* 0xd3018 - Outbound Destination Port Register */
	uint	odatr;		/* 0xd301c - Outbound Destination Attributes Register */
	uint	odcr;		/* 0xd3020 - Outbound Doubleword Count Register */
	uint	eodqhpar;	/* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
	uint	odqhpar;	/* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
	uint	oretr;	        /* 0xd302C - Outbound Retry Error Threshold Register */
	uint	omgr;	        /* 0xd3030 - Outbound Multicast Group Register */
	uint	omlr;	        /* 0xd3034 - Outbound Multicast List Register */
	char	res52[40];
	uint	imr;		/* 0xd3060 - Outbound Mode Register */
	uint	isr;		/* 0xd3064 - Inbound Status Register */
	uint	eidqtpar;	/* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
	uint	idqtpar;	/* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
	uint	eifqhpar;	/* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
	uint	ifqhpar;	/* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
	uint	imirir;	        /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
	char	res53[900];
	uint	oddmr;		/* 0xd3400 - Outbound Doorbell Mode Register */
	uint	oddsr;		/* 0xd3404 - Outbound Doorbell Status Register */
	char	res54[16];
	uint	oddpr;		/* 0xd3418 - Outbound Doorbell Destination Port Register */
	uint	oddatr;		/* 0xd341C - Outbound Doorbell Destination Attributes Register */
	char	res55[12];
	uint	oddretr;	/* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
	char	res56[48];
	uint	idmr;		/* 0xd3460 - Inbound Doorbell Mode Register */
	uint	idsr;		/* 0xd3464 - Inbound Doorbell Status Register */
	uint	iedqtpar;	/* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
	uint	iqtpar;	        /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
	uint	iedqhpar;	/* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
	uint	idqhpar;	/* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
	uint	idmirir;	/* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
	char	res57[100];
	uint	pwmr;		/* 0xd34e0 - Port-Write Mode Register */
	uint	pwsr;		/* 0xd34e4 - Port-Write Status Register */
	uint	epwqbar;	/* 0xd34e8 - Extended Port-Write Queue Base Address Register */
	uint	pwqbar;		/* 0xd34ec - Port-Write Queue Base Address Register */
	char	res58[51984];
} ccsr_rio_t;

/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
typedef struct ccsr_gur {
	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
#define MPC86xx_PORBMSR_HA      0x00060000
	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
	uint	pordevsr;	/* 0xe000c - POR I/O device status regsiter */
#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
	char	res1[12];
	uint	gpporcr;	/* 0xe0020 - General-purpose POR configuration register */
	char	res2[12];
	uint	gpiocr;		/* 0xe0030 - GPIO control register */
	char	res3[12];
	uint	gpoutdr;	/* 0xe0040 - General-purpose output data register */
	char	res4[12];
	uint	gpindr;		/* 0xe0050 - General-purpose input data register */
	char	res5[12];
	uint	pmuxcr;		/* 0xe0060 - Alternate function signal multiplex control */
	char	res6[12];
	uint	devdisr;	/* 0xe0070 - Device disable control */
#define MPC86xx_DEVDISR_PCIEX1  0x80000000
#define MPC86xx_DEVDISR_PCIEX2  0x40000000
	char	res7[12];
	uint	powmgtcsr;	/* 0xe0080 - Power management status and control register */
	char	res8[12];
	uint	mcpsumr;	/* 0xe0090 - Machine check summary register */
	char	res9[12];
	uint	pvr;		/* 0xe00a0 - Processor version register */
	uint	svr;		/* 0xe00a4 - System version register */
	char	res10[3416];
	uint	clkocr;		/* 0xe0e00 - Clock out select register */
	char	res11[12];
	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
	char	res12[12];
	uint	lbcdllcr;	/* 0xe0e20 - LBC DLL control register */
	int	res13[57];
	uint    lynxdcr1;        /* 0xe0f08 - Lynx debug control register 1*/
	int     res14[6];
	uint    ddrioovcr;      /* 0xe0f24 - DDR IO Overdrive Control register */
	char	res15[61656];
} ccsr_gur_t;

typedef struct immap {
	ccsr_local_mcm_t	im_local_mcm;
	ccsr_ddr_t		im_ddr1;
	ccsr_i2c_t		im_i2c;
	ccsr_duart_t		im_duart;
	ccsr_lbc_t		im_lbc;
	ccsr_ddr_t		im_ddr2;
	char                    res1[4096];
	ccsr_pex_t		im_pex1;
	ccsr_pex_t		im_pex2;
	ccsr_ht_t