immap_86xx.h

u-boot-1.1.6 源码包

	uint	pm1mr0;		/* 0x41370 - Performance monitor 1 mask register 0  */
	char	res43[12];
	uint	pm1mr1;		/* 0x41380 - Performance monitor 1 mask register 1  */
	char	res44[12];
	uint	pm2mr0;		/* 0x41390 - Performance monitor 2 mask register 0  */
	char	res45[12];
	uint	pm2mr1;		/* 0x413A0 - Performance monitor 2 mask register 1  */
	char	res46[12];
	uint	pm3mr0;		/* 0x413B0 - Performance monitor 3 mask register 0  */
	char	res47[12];
	uint	pm3mr1;		/* 0x413C0 - Performance monitor 3 mask register 1  */
	char	res48[60];
	uint	msgr0;		/* 0x41400 - Message Register 0 */
	char	res49[12];
	uint	msgr1;		/* 0x41410 - Message Register 1 */
	char	res50[12];
	uint	msgr2;		/* 0x41420 - Message Register 2 */
	char	res51[12];
	uint	msgr3;		/* 0x41430 - Message Register 3 */
	char	res52[204];
	uint	mer;		/* 0x41500 - Message Enable Register */
	char	res53[12];
	uint	msr;		/* 0x41510 - Message Status Register */
	char	res54[60140];
	uint	eivpr0;		/* 0x50000 - External Interrupt Vector/Priority Register 0 */
	char	res55[12];
	uint	eidr0;		/* 0x50010 - External Interrupt Destination Register 0 */
	char	res56[12];
	uint	eivpr1;		/* 0x50020 - External Interrupt Vector/Priority Register 1 */
	char	res57[12];
	uint	eidr1;		/* 0x50030 - External Interrupt Destination Register 1 */
	char	res58[12];
	uint	eivpr2;		/* 0x50040 - External Interrupt Vector/Priority Register 2 */
	char	res59[12];
	uint	eidr2;		/* 0x50050 - External Interrupt Destination Register 2 */
	char	res60[12];
	uint	eivpr3;		/* 0x50060 - External Interrupt Vector/Priority Register 3 */
	char	res61[12];
	uint	eidr3;		/* 0x50070 - External Interrupt Destination Register 3 */
	char	res62[12];
	uint	eivpr4;		/* 0x50080 - External Interrupt Vector/Priority Register 4 */
	char	res63[12];
	uint	eidr4;		/* 0x50090 - External Interrupt Destination Register 4 */
	char	res64[12];
	uint	eivpr5;		/* 0x500a0 - External Interrupt Vector/Priority Register 5 */
	char	res65[12];
	uint	eidr5;		/* 0x500b0 - External Interrupt Destination Register 5 */
	char	res66[12];
	uint	eivpr6;		/* 0x500c0 - External Interrupt Vector/Priority Register 6 */
	char	res67[12];
	uint	eidr6;		/* 0x500d0 - External Interrupt Destination Register 6 */
	char	res68[12];
	uint	eivpr7;		/* 0x500e0 - External Interrupt Vector/Priority Register 7 */
	char	res69[12];
	uint	eidr7;		/* 0x500f0 - External Interrupt Destination Register 7 */
	char	res70[12];
	uint	eivpr8;		/* 0x50100 - External Interrupt Vector/Priority Register 8 */
	char	res71[12];
	uint	eidr8;		/* 0x50110 - External Interrupt Destination Register 8 */
	char	res72[12];
	uint	eivpr9;		/* 0x50120 - External Interrupt Vector/Priority Register 9 */
	char	res73[12];
	uint	eidr9;		/* 0x50130 - External Interrupt Destination Register 9 */
	char	res74[12];
	uint	eivpr10;	/* 0x50140 - External Interrupt Vector/Priority Register 10 */
	char	res75[12];
	uint	eidr10;		/* 0x50150 - External Interrupt Destination Register 10 */
	char	res76[12];
	uint	eivpr11;	/* 0x50160 - External Interrupt Vector/Priority Register 11 */
	char	res77[12];
	uint	eidr11;		/* 0x50170 - External Interrupt Destination Register 11 */
	char	res78[140];
	uint	iivpr0;		/* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
	char	res79[12];
	uint	iidr0;		/* 0x50210 - Internal Interrupt Destination Register 0 */
	char	res80[12];
	uint	iivpr1;		/* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
	char	res81[12];
	uint	iidr1;		/* 0x50230 - Internal Interrupt Destination Register 1 */
	char	res82[12];
	uint	iivpr2;		/* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
	char	res83[12];
	uint	iidr2;		/* 0x50250 - Internal Interrupt Destination Register 2 */
	char	res84[12];
	uint	iivpr3;		/* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
	char	res85[12];
	uint	iidr3;		/* 0x50270 - Internal Interrupt Destination Register 3 */
	char	res86[12];
	uint	iivpr4;		/* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
	char	res87[12];
	uint	iidr4;		/* 0x50290 - Internal Interrupt Destination Register 4 */
	char	res88[12];
	uint	iivpr5;		/* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
	char	res89[12];
	uint	iidr5;		/* 0x502b0 - Internal Interrupt Destination Register 5 */
	char	res90[12];
	uint	iivpr6;		/* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
	char	res91[12];
	uint	iidr6;		/* 0x502d0 - Internal Interrupt Destination Register 6 */
	char	res92[12];
	uint	iivpr7;		/* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
	char	res93[12];
	uint	iidr7;		/* 0x502f0 - Internal Interrupt Destination Register 7 */
	char	res94[12];
	uint	iivpr8;		/* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
	char	res95[12];
	uint	iidr8;		/* 0x50310 - Internal Interrupt Destination Register 8 */
	char	res96[12];
	uint	iivpr9;		/* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
	char	res97[12];
	uint	iidr9;		/* 0x50330 - Internal Interrupt Destination Register 9 */
	char	res98[12];
	uint	iivpr10;	/* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
	char	res99[12];
	uint	iidr10;		/* 0x50350 - Internal Interrupt Destination Register 10 */
	char	res100[12];
	uint	iivpr11;	/* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
	char	res101[12];
	uint	iidr11;		/* 0x50370 - Internal Interrupt Destination Register 11 */
	char	res102[12];
	uint	iivpr12;	/* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
	char	res103[12];
	uint	iidr12;		/* 0x50390 - Internal Interrupt Destination Register 12 */
	char	res104[12];
	uint	iivpr13;	/* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
	char	res105[12];
	uint	iidr13;		/* 0x503b0 - Internal Interrupt Destination Register 13 */
	char	res106[12];
	uint	iivpr14;	/* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
	char	res107[12];
	uint	iidr14;		/* 0x503d0 - Internal Interrupt Destination Register 14 */
	char	res108[12];
	uint	iivpr15;	/* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
	char	res109[12];
	uint	iidr15;		/* 0x503f0 - Internal Interrupt Destination Register 15 */
	char	res110[12];
	uint	iivpr16;	/* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
	char	res111[12];
	uint	iidr16;		/* 0x50410 - Internal Interrupt Destination Register 16 */
	char	res112[12];
	uint	iivpr17;	/* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
	char	res113[12];
	uint	iidr17;		/* 0x50430 - Internal Interrupt Destination Register 17 */
	char	res114[12];
	uint	iivpr18;	/* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
	char	res115[12];
	uint	iidr18;		/* 0x50450 - Internal Interrupt Destination Register 18 */
	char	res116[12];
	uint	iivpr19;	/* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
	char	res117[12];
	uint	iidr19;		/* 0x50470 - Internal Interrupt Destination Register 19 */
	char	res118[12];
	uint	iivpr20;	/* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
	char	res119[12];
	uint	iidr20;		/* 0x50490 - Internal Interrupt Destination Register 20 */
	char	res120[12];
	uint	iivpr21;	/* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
	char	res121[12];
	uint	iidr21;		/* 0x504b0 - Internal Interrupt Destination Register 21 */
	char	res122[12];
	uint	iivpr22;	/* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
	char	res123[12];
	uint	iidr22;		/* 0x504d0 - Internal Interrupt Destination Register 22 */
	char	res124[12];
	uint	iivpr23;	/* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
	char	res125[12];
	uint	iidr23;		/* 0x504f0 - Internal Interrupt Destination Register 23 */
	char	res126[12];
	uint	iivpr24;	/* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
	char	res127[12];
	uint	iidr24;		/* 0x50510 - Internal Interrupt Destination Register 24 */
	char	res128[12];
	uint	iivpr25;	/* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
	char	res129[12];
	uint	iidr25;		/* 0x50530 - Internal Interrupt Destination Register 25 */
	char	res130[12];
	uint	iivpr26;	/* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
	char	res131[12];
	uint	iidr26;		/* 0x50550 - Internal Interrupt Destination Register 26 */
	char	res132[12];
	uint	iivpr27;	/* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
	char	res133[12];
	uint	iidr27;		/* 0x50570 - Internal Interrupt Destination Register 27 */
	char	res134[12];
	uint	iivpr28;	/* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
	char	res135[12];
	uint	iidr28;		/* 0x50590 - Internal Interrupt Destination Register 28 */
	char	res136[12];
	uint	iivpr29;	/* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
	char	res137[12];
	uint	iidr29;		/* 0x505b0 - Internal Interrupt Destination Register 29 */
	char	res138[12];
	uint	iivpr30;	/* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
	char	res139[12];
	uint	iidr30;		/* 0x505d0 - Internal Interrupt Destination Register 30 */
	char	res140[12];
	uint	iivpr31;	/* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
	char	res141[12];
	uint	iidr31;		/* 0x505f0 - Internal Interrupt Destination Register 31 */
	char	res142[4108];
	uint	mivpr0;		/* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
	char	res143[12];
	uint	midr0;		/* 0x51610 - Messaging Interrupt Destination Register 0 */
	char	res144[12];
	uint	mivpr1;		/* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
	char	res145[12];
	uint	midr1;		/* 0x51630 - Messaging Interrupt Destination Register 1 */
	char	res146[12];
	uint	mivpr2;		/* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
	char	res147[12];
	uint	midr2;		/* 0x51650 - Messaging Interrupt Destination Register 2 */
	char	res148[12];
	uint	mivpr3;		/* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
	char	res149[12];
	uint	midr3;		/* 0x51670 - Messaging Interrupt Destination Register 3 */
	char	res150[59852];
	uint	ipi0dr0;	/* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
	char	res151[12];
	uint	ipi0dr1;	/* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
	char	res152[12];
	uint	ipi0dr2;	/* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
	char	res153[12];
	uint	ipi0dr3;	/* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
	char	res154[12];
	uint	ctpr0;		/* 0x60080 - Current Task Priority Register for Processor 0 */
	char	res155[12];
	uint	whoami0;	/* 0x60090 - Who Am I Register for Processor 0 */
	char	res156[12];
	uint	iack0;		/* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
	char	res157[12];
	uint	eoi0;		/* 0x600b0 - End Of Interrupt Register for Processor 0 */
	char	res158[3916];
} ccsr_pic_t;

/* RapidIO Registers(0xc_0000-0xe_0000) */

typedef struct ccsr_rio {
	uint	didcar;		/* 0xc0000 - Device Identity Capability Register */
	uint	dicar;		/* 0xc0004 - Device Information Capability Register */
	uint	aidcar;		/* 0xc0008 - Assembly Identity Capability Register */
	uint	aicar;		/* 0xc000c - Assembly Information Capability Register */
	uint	pefcar;		/* 0xc0010 - Processing Element Features Capability Register */
	uint	spicar;		/* 0xc0014 - Switch Port Information Capability Register */
	uint	socar;		/* 0xc0018 - Source Operations Capability Register */
	uint	docar;		/* 0xc001c - Destination Operations Capability Register */
	char	res1[32];
	uint	msr;		/* 0xc0040 - Mailbox Command And Status Register */
	uint	pwdcsr;		/* 0xc0044 - Port-Write and Doorbell Command And Status Register */
	char	res2[4];
	uint	pellccsr;	/* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
	char	res3[12];
	uint	lcsbacsr;	/* 0xc005c - Local Configuration Space Base Address Command and Status Register */
	uint	bdidcsr;	/* 0xc0060 - Base Device ID Command and Status Register */
	char	res4[4];
	uint	hbdidlcsr;	/* 0xc0068 - Host Base Device ID Lock Command and Status Register */
	uint	ctcsr;		/* 0xc006c - Component Tag Command and Status Register */
	char	res5[144];
	uint	pmbh0csr;	/* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
	char	res6[28];
	uint	pltoccsr;	/* 0xc0120 - Port Link Time-out Control Command and Status Register */
	uint	prtoccsr;	/* 0xc0124 - Port Response Time-out Control Command and Status Register */
	char	res7[20];