immap_86xx.h

u-boot-1.1.6 源码包

	char    res22[4];
	uint    tbase5;         /* 0x2422C - Transmit Descriptor base address of Ring 5 */
	char    res23[4];
	uint    tbase6;         /* 0x24234 - Transmit Descriptor base address of Ring 6 */
	char    res24[4];
	uint    tbase7;         /* 0x2423C - Transmit Descriptor base address of Ring 7 */
	char    res25[192];
	uint	rctrl;		/* 0x24300 - Receive Control Register */
	uint	rstat;		/* 0x24304 - Receive Status Register */
	char	res26[8];
	uint    rxic;           /* 0x24310 - Receive Interrupt Coalecing Register */
	uint    rqueue;         /* 0x24314 - Receive queue control register */
	char	res27[24];
	uint    rbifx;		/* 0x24330 - Receive bit field extract control Register */
	uint    rqfar;		/* 0x24334 - Receive queue filing table address Register */
	uint    rqfcr;		/* 0x24338 - Receive queue filing table control Register */
	uint    rqfpr;      	/* 0x2433c - Receive queue filing table property Register */
	uint	mrblr;		/* 0x24340 - Maximum Receive Buffer Length Register */
	char	res28[56];
	uint    rbdbph;		/* 0x2437C - Receive Data Buffer Pointer High */
	char    res29[4];
	uint	rbptr0;		/* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
	char    res30[4];
	uint	rbptr1;		/* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
	char    res31[4];
	uint	rbptr2;		/* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
	char    res32[4];
	uint	rbptr3;		/* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
	char    res33[4];
	uint	rbptr4;		/* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
	char    res34[4];
	uint	rbptr5;		/* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
	char    res35[4];
	uint	rbptr6;		/* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
	char    res36[4];
	uint	rbptr7;		/* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
	char    res37[64];
	uint	rbaseh;		/* 0x24400 - Receive Descriptor Base Address High 0 */
	uint	rbase0;		/* 0x24404 - Receive Descriptor Base Address of Ring 0 */
	char    res38[4];
	uint	rbase1;		/* 0x2440C - Receive Descriptor Base Address of Ring 1 */
	char    res39[4];
	uint	rbase2;		/* 0x24414 - Receive Descriptor Base Address of Ring 2 */
	char    res40[4];
	uint	rbase3;		/* 0x2441C - Receive Descriptor Base Address of Ring 3 */
	char    res41[4];
	uint	rbase4;		/* 0x24424 - Receive Descriptor Base Address of Ring 4 */
	char    res42[4];
	uint	rbase5;		/* 0x2442C - Receive Descriptor Base Address of Ring 5 */
	char    res43[4];
	uint	rbase6;		/* 0x24434 - Receive Descriptor Base Address of Ring 6 */
	char    res44[4];
	uint	rbase7;		/* 0x2443C - Receive Descriptor Base Address of Ring 7 */
	char    res45[192];
	uint	maccfg1;	/* 0x24500 - MAC Configuration 1 Register */
	uint	maccfg2;	/* 0x24504 - MAC Configuration 2 Register */
	uint	ipgifg;		/* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
	uint	hafdup;		/* 0x2450c - Half Duplex Register */
	uint	maxfrm;		/* 0x24510 - Maximum Frame Length Register */
	char	res46[12];
	uint	miimcfg;	/* 0x24520 - MII Management Configuration Register */
	uint	miimcom;	/* 0x24524 - MII Management Command Register */
	uint	miimadd;	/* 0x24528 - MII Management Address Register */
	uint	miimcon;	/* 0x2452c - MII Management Control Register */
	uint	miimstat;	/* 0x24530 - MII Management Status Register */
	uint	miimind;	/* 0x24534 - MII Management Indicator Register */
	uint    ifctrl;		/* 0x24538 - Interface Contrl Register */
	uint	ifstat;		/* 0x2453c - Interface Status Register */
	uint	macstnaddr1;	/* 0x24540 - Station Address Part 1 Register */
	uint	macstnaddr2;	/* 0x24544 - Station Address Part 2 Register */
	uint    mac01addr1;     /* 0x24548 - MAC exact match address 1, part 1 */
	uint    mac01addr2;     /* 0x2454C - MAC exact match address 1, part 2 */
	uint    mac02addr1;     /* 0x24550 - MAC exact match address 2, part 1 */
	uint    mac02addr2;     /* 0x24554 - MAC exact match address 2, part 2 */
	uint    mac03addr1;     /* 0x24558 - MAC exact match address 3, part 1 */
	uint    mac03addr2;     /* 0x2455C - MAC exact match address 3, part 2 */
	uint    mac04addr1;     /* 0x24560 - MAC exact match address 4, part 1 */
	uint    mac04addr2;     /* 0x24564 - MAC exact match address 4, part 2 */
	uint    mac05addr1;     /* 0x24568 - MAC exact match address 5, part 1 */
	uint    mac05addr2;     /* 0x2456C - MAC exact match address 5, part 2 */
	uint    mac06addr1;     /* 0x24570 - MAC exact match address 6, part 1 */
	uint    mac06addr2;     /* 0x24574 - MAC exact match address 6, part 2 */
	uint    mac07addr1;     /* 0x24578 - MAC exact match address 7, part 1 */
	uint    mac07addr2;     /* 0x2457C - MAC exact match address 7, part 2 */
	uint    mac08addr1;     /* 0x24580 - MAC exact match address 8, part 1 */
	uint    mac08addr2;     /* 0x24584 - MAC exact match address 8, part 2 */
	uint    mac09addr1;     /* 0x24588 - MAC exact match address 9, part 1 */
	uint    mac09addr2;     /* 0x2458C - MAC exact match address 9, part 2 */
	uint    mac10addr1;     /* 0x24590 - MAC exact match address 10, part 1 */
	uint    mac10addr2;     /* 0x24594 - MAC exact match address 10, part 2 */
	uint    mac11addr1;     /* 0x24598 - MAC exact match address 11, part 1 */
	uint    mac11addr2;     /* 0x2459C - MAC exact match address 11, part 2 */
	uint    mac12addr1;     /* 0x245A0 - MAC exact match address 12, part 1 */
	uint    mac12addr2;     /* 0x245A4 - MAC exact match address 12, part 2 */
	uint    mac13addr1;     /* 0x245A8 - MAC exact match address 13, part 1 */
	uint    mac13addr2;     /* 0x245AC - MAC exact match address 13, part 2 */
	uint    mac14addr1;     /* 0x245B0 - MAC exact match address 14, part 1 */
	uint    mac14addr2;     /* 0x245B4 - MAC exact match address 14, part 2 */
	uint    mac15addr1;     /* 0x245B8 - MAC exact match address 15, part 1 */
	uint    mac15addr2;     /* 0x245BC - MAC exact match address 15, part 2 */
	char	res48[192];
	uint	tr64;		/* 0x24680 - Transmit and Receive 64-byte Frame Counter */
	uint	tr127;		/* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
	uint	tr255;		/* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
	uint	tr511;		/* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
	uint	tr1k;		/* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
	uint	trmax;		/* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
	uint	trmgv;		/* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
	uint	rbyt;		/* 0x2469c - Receive Byte Counter */
	uint	rpkt;		/* 0x246a0 - Receive Packet Counter */
	uint	rfcs;		/* 0x246a4 - Receive FCS Error Counter */
	uint	rmca;		/* 0x246a8 - Receive Multicast Packet Counter */
	uint	rbca;		/* 0x246ac - Receive Broadcast Packet Counter */
	uint	rxcf;		/* 0x246b0 - Receive Control Frame Packet Counter */
	uint	rxpf;		/* 0x246b4 - Receive Pause Frame Packet Counter */
	uint	rxuo;		/* 0x246b8 - Receive Unknown OP Code Counter */
	uint	raln;		/* 0x246bc - Receive Alignment Error Counter */
	uint	rflr;		/* 0x246c0 - Receive Frame Length Error Counter */
	uint	rcde;		/* 0x246c4 - Receive Code Error Counter */
	uint	rcse;		/* 0x246c8 - Receive Carrier Sense Error Counter */
	uint	rund;		/* 0x246cc - Receive Undersize Packet Counter */
	uint	rovr;		/* 0x246d0 - Receive Oversize Packet Counter */
	uint	rfrg;		/* 0x246d4 - Receive Fragments Counter */
	uint	rjbr;		/* 0x246d8 - Receive Jabber Counter */
	uint	rdrp;		/* 0x246dc - Receive Drop Counter */
	uint	tbyt;		/* 0x246e0 - Transmit Byte Counter Counter */
	uint	tpkt;		/* 0x246e4 - Transmit Packet Counter */
	uint	tmca;		/* 0x246e8 - Transmit Multicast Packet Counter */
	uint	tbca;		/* 0x246ec - Transmit Broadcast Packet Counter */
	uint	txpf;		/* 0x246f0 - Transmit Pause Control Frame Counter */
	uint	tdfr;		/* 0x246f4 - Transmit Deferral Packet Counter */
	uint	tedf;		/* 0x246f8 - Transmit Excessive Deferral Packet Counter */
	uint	tscl;		/* 0x246fc - Transmit Single Collision Packet Counter */
	uint	tmcl;		/* 0x24700 - Transmit Multiple Collision Packet Counter */
	uint	tlcl;		/* 0x24704 - Transmit Late Collision Packet Counter */
	uint	txcl;		/* 0x24708 - Transmit Excessive Collision Packet Counter */
	uint	tncl;		/* 0x2470c - Transmit Total Collision Counter */
	char	res49[4];
	uint	tdrp;		/* 0x24714 - Transmit Drop Frame Counter */
	uint	tjbr;		/* 0x24718 - Transmit Jabber Frame Counter */
	uint	tfcs;		/* 0x2471c - Transmit FCS Error Counter */
	uint	txcf;		/* 0x24720 - Transmit Control Frame Counter */
	uint	tovr;		/* 0x24724 - Transmit Oversize Frame Counter */
	uint	tund;		/* 0x24728 - Transmit Undersize Frame Counter */
	uint	tfrg;		/* 0x2472c - Transmit Fragments Frame Counter */
	uint	car1;		/* 0x24730 - Carry Register One */
	uint	car2;		/* 0x24734 - Carry Register Two */
	uint	cam1;		/* 0x24738 - Carry Mask Register One */
	uint	cam2;		/* 0x2473c - Carry Mask Register Two */
	uint    rrej;	        /* 0x24740 - Receive filer rejected packet counter */
	char	res50[188];
	uint	iaddr0;		/* 0x24800 - Indivdual address register 0 */
	uint	iaddr1;		/* 0x24804 - Indivdual address register 1 */
	uint	iaddr2;		/* 0x24808 - Indivdual address register 2 */
	uint	iaddr3;		/* 0x2480c - Indivdual address register 3 */
	uint	iaddr4;		/* 0x24810 - Indivdual address register 4 */
	uint	iaddr5;		/* 0x24814 - Indivdual address register 5 */
	uint	iaddr6;		/* 0x24818 - Indivdual address register 6 */
	uint	iaddr7;		/* 0x2481c - Indivdual address register 7 */
	char	res51[96];
	uint	gaddr0;		/* 0x24880 - Global address register 0 */
	uint	gaddr1;		/* 0x24884 - Global address register 1 */
	uint	gaddr2;		/* 0x24888 - Global address register 2 */
	uint	gaddr3;		/* 0x2488c - Global address register 3 */
	uint	gaddr4;		/* 0x24890 - Global address register 4 */
	uint	gaddr5;		/* 0x24894 - Global address register 5 */
	uint	gaddr6;		/* 0x24898 - Global address register 6 */
	uint	gaddr7;		/* 0x2489c - Global address register 7 */
	char	res52[352];
	uint    fifocfg;        /* 0x24A00 - FIFO interface configuration register */
	char    res53[500];
	uint    attr;           /* 0x24BF8 - DMA Attribute register */
	uint    attreli;        /* 0x24BFC - DMA Attribute extract length and index register */
	char    res54[1024];
} ccsr_tsec_t;

/* PIC Registers(0x4_0000-0x6_1000) */

typedef struct ccsr_pic {
	char	res1[64];
	uint	ipidr0;		/* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
	char	res2[12];
	uint	ipidr1;		/* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
	char	res3[12];
	uint	ipidr2;		/* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
	char	res4[12];
	uint	ipidr3;		/* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
	char	res5[12];
	uint	ctpr;		/* 0x40080 - Current Task Priority Register */
	char	res6[12];
	uint	whoami;		/* 0x40090 - Who Am I Register */
	char	res7[12];
	uint	iack;		/* 0x400a0 - Interrupt Acknowledge Register */
	char	res8[12];
	uint	eoi;		/* 0x400b0 - End Of Interrupt Register */
	char	res9[3916];
	uint	frr;		/* 0x41000 - Feature Reporting Register */
	char	res10[28];
	uint	gcr;		/* 0x41020 - Global Configuration Register */
	char	res11[92];
	uint	vir;		/* 0x41080 - Vendor Identification Register */
	char	res12[12];
	uint	pir;		/* 0x41090 - Processor Initialization Register */
	char	res13[12];
	uint	ipivpr0;	/* 0x410a0 - IPI Vector/Priority Register 0 */
	char	res14[12];
	uint	ipivpr1;	/* 0x410b0 - IPI Vector/Priority Register 1 */
	char	res15[12];
	uint	ipivpr2;	/* 0x410c0 - IPI Vector/Priority Register 2 */
	char	res16[12];
	uint	ipivpr3;	/* 0x410d0 - IPI Vector/Priority Register 3 */
	char	res17[12];
	uint	svr;		/* 0x410e0 - Spurious Vector Register */
	char	res18[12];
	uint	tfrr;		/* 0x410f0 - Timer Frequency Reporting Register */
	char	res19[12];
	uint	gtccr0;		/* 0x41100 - Global Timer Current Count Register 0 */
	char	res20[12];
	uint	gtbcr0;		/* 0x41110 - Global Timer Base Count Register 0 */
	char	res21[12];
	uint	gtvpr0;		/* 0x41120 - Global Timer Vector/Priority Register 0 */
	char	res22[12];
	uint	gtdr0;		/* 0x41130 - Global Timer Destination Register 0 */
	char	res23[12];
	uint	gtccr1;		/* 0x41140 - Global Timer Current Count Register 1 */
	char	res24[12];
	uint	gtbcr1;		/* 0x41150 - Global Timer Base Count Register 1 */
	char	res25[12];
	uint	gtvpr1;		/* 0x41160 - Global Timer Vector/Priority Register 1 */
	char	res26[12];
	uint	gtdr1;		/* 0x41170 - Global Timer Destination Register 1 */
	char	res27[12];
	uint	gtccr2;		/* 0x41180 - Global Timer Current Count Register 2 */
	char	res28[12];
	uint	gtbcr2;		/* 0x41190 - Global Timer Base Count Register 2 */
	char	res29[12];
	uint	gtvpr2;		/* 0x411a0 - Global Timer Vector/Priority Register 2 */
	char	res30[12];
	uint	gtdr2;		/* 0x411b0 - Global Timer Destination Register 2 */
	char	res31[12];
	uint	gtccr3;		/* 0x411c0 - Global Timer Current Count Register 3 */
	char	res32[12];
	uint	gtbcr3;		/* 0x411d0 - Global Timer Base Count Register 3 */
	char	res33[12];
	uint	gtvpr3;		/* 0x411e0 - Global Timer Vector/Priority Register 3 */
	char	res34[12];
	uint	gtdr3;		/* 0x411f0 - Global Timer Destination Register 3 */
	char	res35[268];
	uint	tcr;		/* 0x41300 - Timer Control Register */
	char	res36[12];
	uint	irqsr0;		/* 0x41310 - IRQ_OUT Summary Register 0 */
	char	res37[12];
	uint	irqsr1;		/* 0x41320 - IRQ_OUT Summary Register 1 */
	char	res38[12];
	uint	cisr0;		/* 0x41330 - Critical Interrupt Summary Register 0 */
	char	res39[12];
	uint	cisr1;		/* 0x41340 - Critical Interrupt Summary Register 1 */
	char	res40[12];
	uint	pm0mr0;		/* 0x41350 - Performance monitor 0 mask register 0  */
	char	res41[12];
	uint	pm0mr1;		/* 0x41360 - Performance monitor 0 mask register 1  */
	char	res42[12];