immap_86xx.h

u-boot-1.1.6 源码包

	uint	potear2;	/* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
	uint	powbar2;	/* 0x8c48 - PEX Outbound Window Base Address Register 2 */
	char	res8[4];
	uint	powar2;	        /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
	char	res9[12];
	uint	potar3;	        /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
	uint	potear3;	/* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
	uint	powbar3;	/* 0x8c68 - PEX Outbound Window Base Address Register 3 */
	char	res10[4];
	uint	powar3;	        /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
	char	res11[12];
	uint	potar4;	        /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
	uint	potear4;	/* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
	uint	powbar4;	/* 0x8c88 - PEX Outbound Window Base Address Register 4 */
	char	res12[4];
	uint	powar4;	        /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
	char	res13[12];
	char	res14[256];
	uint	pitar3;	        /* 0x8da0 - PEX Inbound Translation Address Register 3  */
	char	res15[4];
	uint	piwbar3;	/* 0x8da8 - PEX Inbound Window Base Address Register 3 */
	uint	piwbear3;	/* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
	uint	piwar3;	        /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
	char	res16[12];
	uint	pitar2;	        /* 0x8dc0 - PEX Inbound Translation Address Register 2  */
	char	res17[4];
	uint	piwbar2;	/* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
	uint	piwbear2;	/* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
	uint	piwar2;	        /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
	char	res18[12];
	uint	pitar1;	        /* 0x8de0 - PEX Inbound Translation Address Register 1  */
	char	res19[4];
	uint	piwbar1;	/* 0x8de8 - PEX Inbound Window Base Address Register 1 */
	uint	piwbear1;
	uint	piwar1;	        /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
	char	res20[12];
	uint	pedr;		/* 0x8e00 - PEX Error Detect Register */
	char    res21[4];
	uint	peer;		/* 0x8e08 - PEX Error Interrupt Enable Register */
	char    res22[4];
	uint	pecdr;		/* 0x8e10 - PEX Error Disable Register */
	char    res23[12];
	uint	peer_stat;	/* 0x8e20 - PEX Error Capture Status Register */
	char    res24[4];
	uint	perr_cap0;	/* 0x8e28 - PEX Error Capture Register 0 */
	uint	perr_cap1;	/* 0x8e2c - PEX Error Capture Register 1 */
	uint	perr_cap2;	/* 0x8e30 - PEX Error Capture Register 2 */
	uint	perr_cap3;	/* 0x8e34 - PEX Error Capture Register 3 */
	char	res25[452];
	char    res26[4];
} ccsr_pex_t;

/* Hyper Transport Register Block (0xA000-0xB000) */
typedef struct ccsr_ht {
	uint    hcfg_addr;      /* 0xa000 - HT Configuration Address register */
	uint    hcfg_data;      /* 0xa004 - HT Configuration Data register */
	char	res1[3064];
	uint    howtar0;        /* 0xac00 - HT Outbound Window 0 Translation register */
	char	res2[12];
	uint    howar0;         /* 0xac10 - HT Outbound Window 0 Attributes register */
	char	res3[12];
	uint    howtar1;        /* 0xac20 - HT Outbound Window 1 Translation register */
	char	res4[4];
	uint    howbar1;        /* 0xac28 - HT Outbound Window 1 Base Address register */
	char	res5[4];
	uint    howar1;         /* 0xac30 - HT Outbound Window 1 Attributes register */
	char	res6[12];
	uint    howtar2;        /* 0xac40 - HT Outbound Window 2 Translation register */
	char	res7[4];
	uint    howbar2;        /* 0xac48 - HT Outbound Window 2 Base Address register */
	char	res8[4];
	uint    howar2;         /* 0xac50 - HT Outbound Window 2 Attributes register */
	char	res9[12];
	uint    howtar3;        /* 0xac60 - HT Outbound Window 3 Translation register */
	char	res10[4];
	uint    howbar3;        /* 0xac68 - HT Outbound Window 3 Base Address register */
	char	res11[4];
	uint    howar3;         /* 0xac70 - HT Outbound Window 3 Attributes  register */
	char	res12[12];
	uint    howtar4;        /* 0xac80 - HT Outbound Window 4 Translation register */
	char	res13[4];
	uint    howbar4;        /* 0xac88 - HT Outbound Window 4 Base Address register */
	char	res14[4];
	uint    howar4;         /* 0xac90 - HT Outbound Window 4 Attributes register */
	char	res15[236];
	uint    hiwtar4;        /* 0xad80 - HT Inbound Window 4 Translation register */
	char	res16[4];
	uint    hiwbar4;        /* 0xad88 - HT Inbound Window 4 Base Address register */
	char	res17[4];
	uint    hiwar4;         /* 0xad90 - HT Inbound Window 4 Attributes register */
	char	res18[12];
	uint    hiwtar3;        /* 0xada0 - HT Inbound Window 3 Translation register */
	char	res19[4];
	uint    hiwbar3;        /* 0xada8 - HT Inbound Window 3 Base Address register */
	char	res20[4];
	uint    hiwar3;         /* 0xadb0 - HT Inbound Window 3 Attributes register */
	char	res21[12];
	uint    hiwtar2;        /* 0xadc0 - HT Inbound Window 2 Translation register */
	char	res22[4];
	uint    hiwbar2;        /* 0xadc8 - HT Inbound Window 2 Base Address register */
	char	res23[4];
	uint    hiwar2;         /* 0xadd0 - HT Inbound Window 2 Attributes register */
	char	res24[12];
	uint    hiwtar1;        /* 0xade0 - HT Inbound Window 1 Translation register */
	char	res25[4];
	uint    hiwbar1;        /* 0xade8 - HT Inbound Window 1 Base Address register */
	char	res26[4];
	uint    hiwar1;         /* 0xadf0 - HT Inbound Window 1 Attributes register */
	char	res27[12];
	uint    hedr;           /* 0xae00 - HT Error Detect register */
	char	res28[4];
	uint    heier;          /* 0xae08 - HT Error Interrupt Enable register */
	char	res29[4];
	uint    hecdr;          /* 0xae10 - HT Error Capture Disbale register */
	char	res30[12];
	uint    hecsr;          /* 0xae20 - HT Error Capture Status register */
	char	res31[4];
	uint    hec0;           /* 0xae28 - HT Error Capture 0 register */
	uint    hec1;           /* 0xae2c - HT Error Capture 1 register */
	uint    hec2;           /* 0xae30 - HT Error Capture 2 register */
	char    res32[460];
} ccsr_ht_t;

/* DMA Registers(0x2_1000-0x2_2000) */
typedef struct ccsr_dma {
	char	res1[256];
	uint	mr0;		/* 0x21100 - DMA 0 Mode Register */
	uint	sr0;		/* 0x21104 - DMA 0 Status Register */
	char	res2[4];
	uint	clndar0;	/* 0x2110c - DMA 0 Current Link Descriptor Address Register */
	uint	satr0;		/* 0x21110 - DMA 0 Source Attributes Register */
	uint	sar0;		/* 0x21114 - DMA 0 Source Address Register */
	uint	datr0;		/* 0x21118 - DMA 0 Destination Attributes Register */
	uint	dar0;		/* 0x2111c - DMA 0 Destination Address Register */
	uint	bcr0;		/* 0x21120 - DMA 0 Byte Count Register */
	char	res3[4];
	uint	nlndar0;	/* 0x21128 - DMA 0 Next Link Descriptor Address Register */
	char	res4[8];
	uint	clabdar0;	/* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
	char	res5[4];
	uint	nlsdar0;	/* 0x2113c - DMA 0 Next List Descriptor Address Register */
	uint	ssr0;		/* 0x21140 - DMA 0 Source Stride Register */
	uint	dsr0;		/* 0x21144 - DMA 0 Destination Stride Register */
	char	res6[56];
	uint	mr1;		/* 0x21180 - DMA 1 Mode Register */
	uint	sr1;		/* 0x21184 - DMA 1 Status Register */
	char	res7[4];
	uint	clndar1;	/* 0x2118c - DMA 1 Current Link Descriptor Address Register */
	uint	satr1;		/* 0x21190 - DMA 1 Source Attributes Register */
	uint	sar1;		/* 0x21194 - DMA 1 Source Address Register */
	uint	datr1;		/* 0x21198 - DMA 1 Destination Attributes Register */
	uint	dar1;		/* 0x2119c - DMA 1 Destination Address Register */
	uint	bcr1;		/* 0x211a0 - DMA 1 Byte Count Register */
	char	res8[4];
	uint	nlndar1;	/* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
	char	res9[8];
	uint	clabdar1;	/* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
	char	res10[4];
	uint	nlsdar1;	/* 0x211bc - DMA 1 Next List Descriptor Address Register */
	uint	ssr1;		/* 0x211c0 - DMA 1 Source Stride Register */
	uint	dsr1;		/* 0x211c4 - DMA 1 Destination Stride Register */
	char	res11[56];
	uint	mr2;		/* 0x21200 - DMA 2 Mode Register */
	uint	sr2;		/* 0x21204 - DMA 2 Status Register */
	char	res12[4];
	uint	clndar2;	/* 0x2120c - DMA 2 Current Link Descriptor Address Register */
	uint	satr2;		/* 0x21210 - DMA 2 Source Attributes Register */
	uint	sar2;		/* 0x21214 - DMA 2 Source Address Register */
	uint	datr2;		/* 0x21218 - DMA 2 Destination Attributes Register */
	uint	dar2;		/* 0x2121c - DMA 2 Destination Address Register */
	uint	bcr2;		/* 0x21220 - DMA 2 Byte Count Register */
	char	res13[4];
	uint	nlndar2;	/* 0x21228 - DMA 2 Next Link Descriptor Address Register */
	char	res14[8];
	uint	clabdar2;	/* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
	char	res15[4];
	uint	nlsdar2;	/* 0x2123c - DMA 2 Next List Descriptor Address Register */
	uint	ssr2;		/* 0x21240 - DMA 2 Source Stride Register */
	uint	dsr2;		/* 0x21244 - DMA 2 Destination Stride Register */
	char	res16[56];
	uint	mr3;		/* 0x21280 - DMA 3 Mode Register */
	uint	sr3;		/* 0x21284 - DMA 3 Status Register */
	char	res17[4];
	uint	clndar3;	/* 0x2128c - DMA 3 Current Link Descriptor Address Register */
	uint	satr3;		/* 0x21290 - DMA 3 Source Attributes Register */
	uint	sar3;		/* 0x21294 - DMA 3 Source Address Register */
	uint	datr3;		/* 0x21298 - DMA 3 Destination Attributes Register */
	uint	dar3;		/* 0x2129c - DMA 3 Destination Address Register */
	uint	bcr3;		/* 0x212a0 - DMA 3 Byte Count Register */
	char	res18[4];
	uint	nlndar3;	/* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
	char	res19[8];
	uint	clabdar3;	/* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
	char	res20[4];
	uint	nlsdar3;	/* 0x212bc - DMA 3 Next List Descriptor Address Register */
	uint	ssr3;		/* 0x212c0 - DMA 3 Source Stride Register */
	uint	dsr3;		/* 0x212c4 - DMA 3 Destination Stride Register */
	char	res21[56];
	uint	dgsr;		/* 0x21300 - DMA General Status Register */
	char	res22[3324];
} ccsr_dma_t;

/* tsec1-4: 24000-28000 */
typedef struct ccsr_tsec {
	uint    id; 		/* 0x24000 - Controller ID Register */
	char	res1[12];
	uint	ievent;		/* 0x24010 - Interrupt Event Register */
	uint	imask;		/* 0x24014 - Interrupt Mask Register */
	uint	edis;		/* 0x24018 - Error Disabled Register */
	char	res2[4];
	uint	ecntrl;		/* 0x24020 - Ethernet Control Register */
	char    res2_1[4];
	uint	ptv;		/* 0x24028 - Pause Time Value Register */
	uint	dmactrl;	/* 0x2402c - DMA Control Register */
	uint	tbipa;		/* 0x24030 - TBI PHY Address Register */
	char	res3[88];
	uint	fifo_tx_thr;	/* 0x2408c - FIFO transmit threshold register */
	char	res4[8];
	uint	fifo_tx_starve;	/* 0x24098 - FIFO transmit starve register */
	uint	fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
	char    res4_1[4];
	uint    fifo_rx_pause;  /* 0x240a4 - FIFO receive pause threshold register */
	uint    fifo_rx_alarm;  /* 0x240a8 - FIFO receive alarm threshold register */
	char	res5[84];
	uint	tctrl;		/* 0x24100 - Transmit Control Register */
	uint	tstat;		/* 0x24104 - Transmit Status Register */
	uint    dfvlan;		/* 0x24108 - Default VLAN control word */
	char    res6[4];
	uint    txic;		/* 0x24110 - Transmit interrupt coalescing Register */
	uint    tqueue;         /* 0x24114 - Transmit Queue Control Register */
	char	res7[40];
	uint    tr03wt;         /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
	uint    tw47wt;         /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
	char    res8[52];
	uint	tbdbph;	        /* 0x2417c - Transmit Data Buffer Pointer High Register */
	char    res9[4];
	uint    tbptr0;         /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
	char    res10[4];
	uint    tbptr1;         /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
	char    res11[4];
	uint    tbptr2;         /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
	char    res12[4];
	uint    tbptr3;         /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
	char    res13[4];
	uint    tbptr4;         /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
	char    res14[4];
	uint    tbptr5;         /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
	char    res15[4];
	uint    tbptr6;         /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
	char    res16[4];
	uint    tbptr7;         /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
	char    res17[64];
	uint	tbaseh;		/* 0x24200 - Transmit Descriptor Base Address High Register */
	uint	tbase0;		/* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
	char    res18[4];
	uint    tbase1;         /* 0x2420C - Transmit Descriptor base address of Ring 1 */
	char    res19[4];
	uint    tbase2;         /* 0x24214 - Transmit Descriptor base address of Ring 2 */
	char    res20[4];
	uint    tbase3;         /* 0x2421C - Transmit Descriptor base address of Ring 3 */
	char    res21[4];
	uint    tbase4;         /* 0x24224 - Transmit Descriptor base address of Ring 4 */