immap_86xx.h

u-boot-1.1.6 源码包

/*
 * MPC86xx Internal Memory Map
 *
 * Copyright(c) 2004 Freescale Semiconductor
 * Jeff Brown ([e-mail])
 * Srikanth Srinivasan ([e-mail])
 *
 */

#ifndef __IMMAP_86xx__
#define __IMMAP_86xx__

#include <asm/types.h>
#include <asm/fsl_i2c.h>

/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
typedef struct ccsr_local_mcm {
	uint	ccsrbar;	/* 0x0 - Control Configuration Status Registers Base Address Register */
	char	res1[4];
	uint	altcbar;	/* 0x8 - Alternate Configuration Base Address Register */
	char	res2[4];
	uint	altcar;		/* 0x10 - Alternate Configuration Attribute Register */
	char	res3[12];
	uint	bptr;		/* 0x20 - Boot Page Translation Register */
	char	res4[3044];
	uint	lawbar0;	/* 0xc08 - Local Access Window 0 Base Address Register */
	char	res5[4];
	uint	lawar0;		/* 0xc10 - Local Access Window 0 Attributes Register */
	char	res6[20];
	uint	lawbar1;	/* 0xc28 - Local Access Window 1 Base Address Register */
	char	res7[4];
	uint	lawar1;		/* 0xc30 - Local Access Window 1 Attributes Register */
	char	res8[20];
	uint	lawbar2;	/* 0xc48 - Local Access Window 2 Base Address Register */
	char	res9[4];
	uint	lawar2;		/* 0xc50 - Local Access Window 2 Attributes Register */
	char	res10[20];
	uint	lawbar3;	/* 0xc68 - Local Access Window 3 Base Address Register */
	char	res11[4];
	uint	lawar3;		/* 0xc70 - Local Access Window 3 Attributes Register */
	char	res12[20];
	uint	lawbar4;	/* 0xc88 - Local Access Window 4 Base Address Register */
	char	res13[4];
	uint	lawar4;		/* 0xc90 - Local Access Window 4 Attributes Register */
	char	res14[20];
	uint	lawbar5;	/* 0xca8 - Local Access Window 5 Base Address Register */
	char	res15[4];
	uint	lawar5;		/* 0xcb0 - Local Access Window 5 Attributes Register */
	char	res16[20];
	uint	lawbar6;	/* 0xcc8 - Local Access Window 6 Base Address Register */
	char	res17[4];
	uint	lawar6;		/* 0xcd0 - Local Access Window 6 Attributes Register */
	char	res18[20];
	uint	lawbar7;	/* 0xce8 - Local Access Window 7 Base Address Register */
	char	res19[4];
	uint	lawar7;		/* 0xcf0 - Local Access Window 7 Attributes Register */
	char	res20[20];
	uint	lawbar8;	/* 0xd08 - Local Access Window 8 Base Address Register */
	char	res21[4];
	uint	lawar8;		/* 0xd10 - Local Access Window 8 Attributes Register */
	char	res22[20];
	uint	lawbar9;	/* 0xd28 - Local Access Window 9 Base Address Register */
	char	res23[4];
	uint	lawar9;		/* 0xd30 - Local Access Window 9 Attributes Register */
	char	res24[716];
	uint	abcr;		/* 0x1000 - MCM CCB Address Configuration Register */
	char	res25[4];
	uint    dbcr;           /* 0x1008 - MCM MPX data bus Configuration Register */
	char	res26[4];
	uint	pcr;		/* 0x1010 - MCM CCB Port Configuration Register */
	char	res27[44];
	uint	hpmr0;		/* 0x1040 - MCM HPM Threshold Count Register 0 */
	uint	hpmr1;		/* 0x1044 - MCM HPM Threshold Count Register 1 */
	uint	hpmr2;		/* 0x1048 - MCM HPM Threshold Count Register 2 */
	uint	hpmr3;		/* 0x104c - MCM HPM Threshold Count Register 3 */
	char	res28[16];
	uint	hpmr4;		/* 0x1060 - MCM HPM Threshold Count Register 4 */
	uint	hpmr5;		/* 0x1064 - MCM HPM Threshold Count Register 5 */
	uint	hpmccr;		/* 0x1068 - MCM HPM Cycle Count Register */
	char	res29[3476];
	uint	edr;		/* 0x1e00 - MCM Error Detect Register */
	char	res30[4];
	uint	eer;		/* 0x1e08 - MCM Error Enable Register */
	uint	eatr;		/* 0x1e0c - MCM Error Attributes Capture Register */
	uint	eladr;		/* 0x1e10 - MCM Error Low Address Capture Register */
	uint	ehadr;		/* 0x1e14 - MCM Error High Address Capture Register */
	char	res31[488];
} ccsr_local_mcm_t;

/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */

typedef struct ccsr_ddr {
	uint	cs0_bnds;		/* 0x2000 - DDR Chip Select 0 Memory Bounds */
	char	res1[4];
	uint	cs1_bnds;		/* 0x2008 - DDR Chip Select 1 Memory Bounds */
	char	res2[4];
	uint	cs2_bnds;		/* 0x2010 - DDR Chip Select 2 Memory Bounds */
	char	res3[4];
	uint	cs3_bnds;		/* 0x2018 - DDR Chip Select 3 Memory Bounds */
	char	res4[4];
	uint	cs4_bnds;		/* 0x2020 - DDR Chip Select 4 Memory Bounds */
	char	res5[4];
	uint	cs5_bnds;		/* 0x2028 - DDR Chip Select 5 Memory Bounds */
	char	res6[84];
	uint	cs0_config;		/* 0x2080 - DDR Chip Select Configuration */
	uint	cs1_config;		/* 0x2084 - DDR Chip Select Configuration */
	uint	cs2_config;		/* 0x2088 - DDR Chip Select Configuration */
	uint	cs3_config;		/* 0x208c - DDR Chip Select Configuration */
	uint	cs4_config;		/* 0x2090 - DDR Chip Select Configuration */
	uint	cs5_config;		/* 0x2094 - DDR Chip Select Configuration */
	char	res7[104];
	uint    ext_refrec;             /* 0x2100 - DDR SDRAM extended refresh recovery */
	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
	uint	sdram_cfg_1;		/* 0x2110 - DDR SDRAM Control Configuration 1 */
	uint    sdram_cfg_2;            /* 0x2114 - DDR SDRAM Control Configuration 2 */
	uint	sdram_mode_1;		/* 0x2118 - DDR SDRAM Mode Configuration 1 */
	uint    sdram_mode_2;		/* 0x211c - DDR SDRAM Mode Configuration 2 */
	uint    sdram_mode_cntl;        /* 0x2120 - DDR SDRAM Mode Control */
	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */
	uint    sdram_data_init; 	/* 0x2128 - DDR SDRAM Data Initialization */
	char	res8[4];
	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
	char    res9[12];
	uint    sdram_ocd_cntl;		/* 0x2140 - DDR SDRAM OCD Control */
	uint    sdram_ocd_status;	/* 0x2144 - DDR SDRAM OCD Status */
	uint    init_addr;		/* 0x2148 - DDR training initialzation address */
	uint    init_addr_ext;		/* 0x214C - DDR training initialzation extended address */
	char    res10[2728];
	uint    ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
	uint    ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */
	char	res11[512];
	uint	data_err_inject_hi;	/* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
	uint	data_err_inject_lo;	/* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
	uint	ecc_err_inject;		/* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
	char	res12[20];
	uint	capture_data_hi;	/* 0x2e20 - DDR Memory Data Path Read Capture High */
	uint	capture_data_lo;	/* 0x2e24 - DDR Memory Data Path Read Capture Low */
	uint	capture_ecc;		/* 0x2e28 - DDR Memory Data Path Read Capture ECC */
	char	res13[20];
	uint	err_detect;		/* 0x2e40 - DDR Memory Error Detect */
	uint	err_disable;		/* 0x2e44 - DDR Memory Error Disable */
	uint	err_int_en;		/* 0x2e48 - DDR Memory Error Interrupt Enable */
	uint	capture_attributes;	/* 0x2e4c - DDR Memory Error Attributes Capture */
	uint	capture_address;	/* 0x2e50 - DDR Memory Error Address Capture */
	uint	capture_ext_address;	/* 0x2e54 - DDR Memory Error Extended Address Capture */
	uint	err_sbe;		/* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
	char	res14[164];
	uint	debug_1;		/* 0x2f00 */
	uint	debug_2;
	uint	debug_3;
	uint	debug_4;
	uint	debug_5;
	char	res15[236];
} ccsr_ddr_t;


/* Daul I2C Registers(0x3000-0x4000) */
typedef struct ccsr_i2c {
	struct fsl_i2c	i2c[2];
	u8	res[4096 - 2 * sizeof(struct fsl_i2c)];
} ccsr_i2c_t;

/* DUART Registers(0x4000-0x5000) */
typedef struct ccsr_duart {
	char	res1[1280];
	u_char	urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
	u_char	uier1_udmb1;	/* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
	u_char	uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
	u_char	ulcr1;		/* 0x4503 - UART1 Line Control Register */
	u_char	umcr1;		/* 0x4504 - UART1 Modem Control Register */
	u_char	ulsr1;		/* 0x4505 - UART1 Line Status Register */
	u_char	umsr1;		/* 0x4506 - UART1 Modem Status Register */
	u_char	uscr1;		/* 0x4507 - UART1 Scratch Register */
	char	res2[8];
	u_char	udsr1;		/* 0x4510 - UART1 DMA Status Register */
	char	res3[239];
	u_char	urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
	u_char	uier2_udmb2;	/* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
	u_char	uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
	u_char	ulcr2;		/* 0x4603 - UART2 Line Control Register */
	u_char	umcr2;		/* 0x4604 - UART2 Modem Control Register */
	u_char	ulsr2;		/* 0x4605 - UART2 Line Status Register */
	u_char	umsr2;		/* 0x4606 - UART2 Modem Status Register */
	u_char	uscr2;		/* 0x4607 - UART2 Scratch Register */
	char	res4[8];
	u_char	udsr2;		/* 0x4610 - UART2 DMA Status Register */
	char	res5[2543];
} ccsr_duart_t;


/* Local Bus Controller Registers(0x5000-0x6000) */
typedef struct ccsr_lbc {
	uint	br0;		/* 0x5000 - LBC Base Register 0 */
	uint	or0;		/* 0x5004 - LBC Options Register 0 */
	uint	br1;		/* 0x5008 - LBC Base Register 1 */
	uint	or1;		/* 0x500c - LBC Options Register 1 */
	uint	br2;		/* 0x5010 - LBC Base Register 2 */
	uint	or2;		/* 0x5014 - LBC Options Register 2 */
	uint	br3;		/* 0x5018 - LBC Base Register 3 */
	uint	or3;		/* 0x501c - LBC Options Register 3 */
	uint	br4;		/* 0x5020 - LBC Base Register 4 */
	uint	or4;		/* 0x5024 - LBC Options Register 4 */
	uint	br5;		/* 0x5028 - LBC Base Register 5 */
	uint	or5;		/* 0x502c - LBC Options Register 5 */
	uint	br6;		/* 0x5030 - LBC Base Register 6 */
	uint	or6;		/* 0x5034 - LBC Options Register 6 */
	uint	br7;		/* 0x5038 - LBC Base Register 7 */
	uint	or7;		/* 0x503c - LBC Options Register 7 */
	char	res1[40];
	uint	mar;		/* 0x5068 - LBC UPM Address Register */
	char	res2[4];
	uint	mamr;		/* 0x5070 - LBC UPMA Mode Register */
	uint	mbmr;		/* 0x5074 - LBC UPMB Mode Register */
	uint	mcmr;		/* 0x5078 - LBC UPMC Mode Register */
	char	res3[8];
	uint	mrtpr;		/* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
	uint	mdr;		/* 0x5088 - LBC UPM Data Register */
	char	res4[8];
	uint	lsdmr;		/* 0x5094 - LBC SDRAM Mode Register */
	char	res5[8];
	uint	lurt;		/* 0x50a0 - LBC UPM Refresh Timer */
	uint	lsrt;		/* 0x50a4 - LBC SDRAM Refresh Timer */
	char	res6[8];
	uint	ltesr;		/* 0x50b0 - LBC Transfer Error Status Register */
	uint	ltedr;		/* 0x50b4 - LBC Transfer Error Disable Register */
	uint	lteir;		/* 0x50b8 - LBC Transfer Error Interrupt Register */
	uint	lteatr;		/* 0x50bc - LBC Transfer Error Attributes Register */
	uint	ltear;		/* 0x50c0 - LBC Transfer Error Address Register */
	char	res7[12];
	uint	lbcr;		/* 0x50d0 - LBC Configuration Register */
	uint	lcrr;		/* 0x50d4 - LBC Clock Ratio Register */
	char	res8[3880];
} ccsr_lbc_t;

/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
typedef struct ccsr_pex {
	uint	cfg_addr;	/* 0x8000 - PEX Configuration Address Register */
	uint	cfg_data;	/* 0x8004 - PEX Configuration Data Register */
	char	res1[4];
	uint	out_comp_to;	/* 0x800C - PEX Outbound Completion Timeout Register */
	char	res2[16];
	uint	pme_msg_det;	/* 0x8020 - PEX PME & message detect register */
	uint    pme_msg_int_en;	/* 0x8024 - PEX PME & message interrupt enable register */
	uint    pme_msg_dis;	/* 0x8028 - PEX PME & message disable register */
	uint    pm_command;	/* 0x802c - PEX PM Command register */
	char	res3[3016];
	uint    block_rev1;	/* 0x8bf8 - PEX Block Revision register 1 */
	uint    block_rev2;	/* 0x8bfc - PEX Block Revision register 2 */
	uint	potar0;	        /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
	uint	potear0;	/* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
	char	res4[8];
	uint	powar0;	        /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
	char	res5[12];
	uint	potar1;	        /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
	uint	potear1;	/* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
	uint	powbar1;	/* 0x8c28 - PEX Outbound Window Base Address Register 1 */
	char	res6[4];
	uint	powar1;	        /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
	char	res7[12];
	uint	potar2;	        /* 0x8c40 - PEX Outbound Transaction Address Register 2 */