📄 ppc4xx_enet.h
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/*----------------------------------------------------------------------------+|| This source code has been made available to you by IBM on an AS-IS| basis. Anyone receiving this source is licensed under IBM| copyrights to use it in any way he or she deems fit, including| copying it, modifying it, compiling it, and redistributing it either| with or without modifications. No license under IBM patents or| patent applications is to be implied by the copyright license.|| Any user of this software should understand that IBM cannot provide| technical support for this software and will not be responsible for| any consequences resulting from the use of this software.|| Any person who transfers this source code or any derivative work| must include the IBM copyright notice, this paragraph, and the| preceding two paragraphs in the transferred software.|| COPYRIGHT I B M CORPORATION 1999| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M+----------------------------------------------------------------------------*//*----------------------------------------------------------------------------+|| File Name: enetemac.h|| Function: Header file for the EMAC3 macro on the 405GP.|| Author: Mark Wisner|| Change Activity-|| Date Description of Change BY| --------- --------------------- ---| 29-Apr-99 Created MKW|+----------------------------------------------------------------------------*//*----------------------------------------------------------------------------+| 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com| ported to handle 440GP and 440GX multiple EMACs+----------------------------------------------------------------------------*/#ifndef _PPC4XX_ENET_H_#define _PPC4XX_ENET_H_#include <net.h>#include "405_mal.h"/*-----------------------------------------------------------------------------+| General enternet defines. 802 frames are not supported.+-----------------------------------------------------------------------------*/#define ENET_ADDR_LENGTH 6#define ENET_ARPTYPE 0x806#define ARP_REQUEST 1#define ARP_REPLY 2#define ENET_IPTYPE 0x800#define ARP_CACHE_SIZE 5#define NUM_TX_BUFF 1#define NUM_RX_BUFF PKTBUFSRXstruct enet_frame { unsigned char dest_addr[ENET_ADDR_LENGTH]; unsigned char source_addr[ENET_ADDR_LENGTH]; unsigned short type; unsigned char enet_data[1];};struct arp_entry { unsigned long inet_address; unsigned char mac_address[ENET_ADDR_LENGTH]; unsigned long valid; unsigned long sec; unsigned long nsec;};/* Statistic Areas */#define MAX_ERR_LOG 10typedef struct emac_stats_st{ /* Statistic Block */ int data_len_err; int rx_frames; int rx; int rx_prot_err; int int_err; int pkts_tx; int pkts_rx; int pkts_handled; short tx_err_log[MAX_ERR_LOG]; short rx_err_log[MAX_ERR_LOG];} EMAC_STATS_ST, *EMAC_STATS_PST;/* Structure containing variables used by the shared code (4xx_enet.c) */typedef struct emac_4xx_hw_st { uint32_t hw_addr; /* EMAC offset */ uint32_t tah_addr; /* TAH offset */ uint32_t phy_id; uint32_t phy_addr; uint32_t original_fc; uint32_t txcw; uint32_t autoneg_failed; uint32_t emac_ier; volatile mal_desc_t *tx; volatile mal_desc_t *rx; bd_t *bis; /* for eth_init upon mal error */ mal_desc_t *alloc_tx_buf; mal_desc_t *alloc_rx_buf; char *txbuf_ptr; uint16_t devnum; int get_link_status; int tbi_compatibility_en; int tbi_compatibility_on; int fc_send_xon; int report_tx_early; int first_init; int tx_err_index; int rx_err_index; int rx_slot; /* MAL Receive Slot */ int rx_i_index; /* Receive Interrupt Queue Index */ int rx_u_index; /* Receive User Queue Index */ int tx_slot; /* MAL Transmit Slot */ int tx_i_index; /* Transmit Interrupt Queue Index */ int tx_u_index; /* Transmit User Queue Index */ int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */ int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */ int is_receiving; /* sync with eth interrupt */ int print_speed; /* print speed message upon start */ EMAC_STATS_ST stats;} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;#if defined(CONFIG_440GX)#define EMAC_NUM_DEV 4#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \ defined(CONFIG_NET_MULTI) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)#define EMAC_NUM_DEV 2#else#define EMAC_NUM_DEV 1#endif#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */#define EMAC_STACR_OC_MASK (0x00008000)#else#define EMAC_STACR_OC_MASK (0x00000000)#endif#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)#define SDR0_PFC1_EM_1000 (0x00200000)#endif/*ZMII Bridge Register addresses */#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)#else#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)#endif#define ZMII_FER (ZMII_BASE)#define ZMII_SSR (ZMII_BASE + 4)#define ZMII_SMIISR (ZMII_BASE + 8)#define ZMII_RMII 0x22000000#define ZMII_MDI0 0x80000000/* ZMII FER Register Bit Definitions */#define ZMII_FER_DIS (0x0)#define ZMII_FER_MDI (0x8)#define ZMII_FER_SMII (0x4)#define ZMII_FER_RMII (0x2)#define ZMII_FER_MII (0x1)#define ZMII_FER_RSVD11 (0x00200000)#define ZMII_FER_RSVD10 (0x00100000)#define ZMII_FER_RSVD14_31 (0x0003FFFF)#define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)/* ZMII Speed Selection Register Bit Definitions */#define ZMII_SSR_SCI (0x4)#define ZMII_SSR_FSS (0x2)#define ZMII_SSR_SP (0x1)#define ZMII_SSR_RSVD16_31 (0x0000FFFF)#define ZMII_SSR_V(__x) (((3 - __x) * 4) + 16)/* ZMII SMII Status Register Bit Definitions */#define ZMII_SMIISR_E1 (0x80)#define ZMII_SMIISR_EC (0x40)#define ZMII_SMIISR_EN (0x20)#define ZMII_SMIISR_EJ (0x10)#define ZMII_SMIISR_EL (0x08)#define ZMII_SMIISR_ED (0x04)#define ZMII_SMIISR_ES (0x02)#define ZMII_SMIISR_EF (0x01)#define ZMII_SMIISR_V(__x) ((3 - __x) * 8)/* RGMII Register Addresses */#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000)#else#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790)#endif#define RGMII_FER (RGMII_BASE + 0x00)#define RGMII_SSR (RGMII_BASE + 0x04)/* RGMII Function Enable (FER) Register Bit Definitions *//* Note: for EMAC 2 and 3 only, 440GX only */#define RGMII_FER_DIS (0x00)#define RGMII_FER_RTBI (0x04)#define RGMII_FER_RGMII (0x05)#define RGMII_FER_TBI (0x06)#define RGMII_FER_GMII (0x07)#define RGMII_FER_V(__x) ((__x - 2) * 4)/* RGMII Speed Selection Register Bit Definitions */#define RGMII_SSR_SP_10MBPS (0x00)#define RGMII_SSR_SP_100MBPS (0x02)#define RGMII_SSR_SP_1000MBPS (0x04)#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)#define RGMII_SSR_V(__x) ((__x) * 8)#else#define RGMII_SSR_V(__x) ((__x -2) * 8)#endif/*---------------------------------------------------------------------------+| TCP/IP Acceleration Hardware (TAH) 440GX Only+---------------------------------------------------------------------------*/#if defined(CONFIG_440GX)#define TAH_BASE (CFG_PERIPHERAL_BASE + 0x0B50)#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) *//* TAH Revision */#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */#define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */#define TAH_REV_RN_V (8)#define TAH_REV_BN_V (0)/* TAH Mode Register */#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */#define TAH_MR_SR (0x40000000) /* Software reset */#define TAH_MR_ST (0x3F000000) /* Send Threshold */⌨️ 快捷键说明
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