📄 mpc5xxx.h

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/* * include/asm-ppc/mpc5xxx.h * * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx * embedded cpu chips * * 2003 (c) MontaVista, Software, Inc. * Author: Dale Farnsworth <dfarnsworth@mvista.com> * * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef __ASMPPC_MPC5XXX_H#define __ASMPPC_MPC5XXX_H/* Processor name */#if defined(CONFIG_MPC5200)#define CPU_ID_STR	"MPC5200"#elif defined(CONFIG_MGT5100)#define CPU_ID_STR	"MGT5100"#endif/* Exception offsets (PowerPC standard) */#define EXC_OFF_SYS_RESET	0x0100/* useful macros for manipulating CSx_START/STOP */#if defined(CONFIG_MGT5100)#define START_REG(start)	((start) >> 15)#define STOP_REG(start, size)	(((start) + (size) - 1) >> 15)#elif defined(CONFIG_MPC5200)#define START_REG(start)	((start) >> 16)#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)#endif/* Internal memory map */#define MPC5XXX_CS0_START	(CFG_MBAR + 0x0004)#define MPC5XXX_CS0_STOP	(CFG_MBAR + 0x0008)#define MPC5XXX_CS1_START	(CFG_MBAR + 0x000c)#define MPC5XXX_CS1_STOP	(CFG_MBAR + 0x0010)#define MPC5XXX_CS2_START	(CFG_MBAR + 0x0014)#define MPC5XXX_CS2_STOP	(CFG_MBAR + 0x0018)#define MPC5XXX_CS3_START	(CFG_MBAR + 0x001c)#define MPC5XXX_CS3_STOP	(CFG_MBAR + 0x0020)#define MPC5XXX_CS4_START	(CFG_MBAR + 0x0024)#define MPC5XXX_CS4_STOP	(CFG_MBAR + 0x0028)#define MPC5XXX_CS5_START	(CFG_MBAR + 0x002c)#define MPC5XXX_CS5_STOP	(CFG_MBAR + 0x0030)#define MPC5XXX_BOOTCS_START	(CFG_MBAR + 0x004c)#define MPC5XXX_BOOTCS_STOP	(CFG_MBAR + 0x0050)#define MPC5XXX_ADDECR		(CFG_MBAR + 0x0054)#if defined(CONFIG_MGT5100)#define MPC5XXX_SDRAM_START	(CFG_MBAR + 0x0034)#define MPC5XXX_SDRAM_STOP	(CFG_MBAR + 0x0038)#define MPC5XXX_PCI1_START	(CFG_MBAR + 0x003c)#define MPC5XXX_PCI1_STOP	(CFG_MBAR + 0x0040)#define MPC5XXX_PCI2_START	(CFG_MBAR + 0x0044)#define MPC5XXX_PCI2_STOP	(CFG_MBAR + 0x0048)#elif defined(CONFIG_MPC5200)#define MPC5XXX_CS6_START	(CFG_MBAR + 0x0058)#define MPC5XXX_CS6_STOP	(CFG_MBAR + 0x005c)#define MPC5XXX_CS7_START	(CFG_MBAR + 0x0060)#define MPC5XXX_CS7_STOP	(CFG_MBAR + 0x0064)#define MPC5XXX_SDRAM_CS0CFG	(CFG_MBAR + 0x0034)#define MPC5XXX_SDRAM_CS1CFG	(CFG_MBAR + 0x0038)#endif#define MPC5XXX_SDRAM		(CFG_MBAR + 0x0100)#define MPC5XXX_CDM		(CFG_MBAR + 0x0200)#define MPC5XXX_LPB		(CFG_MBAR + 0x0300)#define MPC5XXX_ICTL		(CFG_MBAR + 0x0500)#define MPC5XXX_GPT		(CFG_MBAR + 0x0600)#define MPC5XXX_GPIO		(CFG_MBAR + 0x0b00)#define MPC5XXX_WU_GPIO         (CFG_MBAR + 0x0c00)#define MPC5XXX_PCI		(CFG_MBAR + 0x0d00)#define MPC5XXX_SPI		(CFG_MBAR + 0x0f00)#define MPC5XXX_USB		(CFG_MBAR + 0x1000)#define MPC5XXX_SDMA		(CFG_MBAR + 0x1200)#define MPC5XXX_XLBARB		(CFG_MBAR + 0x1f00)#if defined(CONFIG_MGT5100)#define	MPC5XXX_PSC1		(CFG_MBAR + 0x2000)#define	MPC5XXX_PSC2		(CFG_MBAR + 0x2400)#define	MPC5XXX_PSC3		(CFG_MBAR + 0x2800)#elif defined(CONFIG_MPC5200)#define	MPC5XXX_PSC1		(CFG_MBAR + 0x2000)#define	MPC5XXX_PSC2		(CFG_MBAR + 0x2200)#define	MPC5XXX_PSC3		(CFG_MBAR + 0x2400)#define	MPC5XXX_PSC4		(CFG_MBAR + 0x2600)#define	MPC5XXX_PSC5		(CFG_MBAR + 0x2800)#define	MPC5XXX_PSC6		(CFG_MBAR + 0x2c00)#endif#define	MPC5XXX_FEC		(CFG_MBAR + 0x3000)#define MPC5XXX_ATA             (CFG_MBAR + 0x3A00)#define MPC5XXX_I2C1		(CFG_MBAR + 0x3D00)#define MPC5XXX_I2C2		(CFG_MBAR + 0x3D40)#if defined(CONFIG_MGT5100)#define MPC5XXX_SRAM		(CFG_MBAR + 0x4000)#define MPC5XXX_SRAM_SIZE	(8*1024)#elif defined(CONFIG_MPC5200)#define MPC5XXX_SRAM		(CFG_MBAR + 0x8000)#define MPC5XXX_SRAM_SIZE	(16*1024)#endif/* SDRAM Controller */#define MPC5XXX_SDRAM_MODE	(MPC5XXX_SDRAM + 0x0000)#define MPC5XXX_SDRAM_CTRL	(MPC5XXX_SDRAM + 0x0004)#define MPC5XXX_SDRAM_CONFIG1	(MPC5XXX_SDRAM + 0x0008)#define MPC5XXX_SDRAM_CONFIG2	(MPC5XXX_SDRAM + 0x000c)#if defined(CONFIG_MGT5100)#define MPC5XXX_SDRAM_XLBSEL	(MPC5XXX_SDRAM + 0x0010)#endif#define MPC5XXX_SDRAM_SDELAY	(MPC5XXX_SDRAM + 0x0090)/* Clock Distribution Module */#define MPC5XXX_CDM_JTAGID	(MPC5XXX_CDM + 0x0000)#define MPC5XXX_CDM_PORCFG	(MPC5XXX_CDM + 0x0004)#define MPC5XXX_CDM_CFG		(MPC5XXX_CDM + 0x000c)#define MPC5XXX_CDM_48_FDC	(MPC5XXX_CDM + 0x0010)#define MPC5XXX_CDM_SRESET	(MPC5XXX_CDM + 0x0020)/* Local Plus Bus interface */#define MPC5XXX_CS0_CFG		(MPC5XXX_LPB + 0x0000)#define MPC5XXX_CS1_CFG		(MPC5XXX_LPB + 0x0004)#define MPC5XXX_CS2_CFG		(MPC5XXX_LPB + 0x0008)#define MPC5XXX_CS3_CFG		(MPC5XXX_LPB + 0x000c)#define MPC5XXX_CS4_CFG		(MPC5XXX_LPB + 0x0010)#define MPC5XXX_CS5_CFG		(MPC5XXX_LPB + 0x0014)#define MPC5XXX_BOOTCS_CFG	MPC5XXX_CS0_CFG#define MPC5XXX_CS_CTRL		(MPC5XXX_LPB + 0x0018)#define MPC5XXX_CS_STATUS	(MPC5XXX_LPB + 0x001c)#if defined(CONFIG_MPC5200)#define MPC5XXX_CS6_CFG		(MPC5XXX_LPB + 0x0020)#define MPC5XXX_CS7_CFG		(MPC5XXX_LPB + 0x0024)#define MPC5XXX_CS_BURST	(MPC5XXX_LPB + 0x0028)#define MPC5XXX_CS_DEADCYCLE	(MPC5XXX_LPB + 0x002c)#endif#if defined(CONFIG_MPC5200)/* XLB Arbiter registers */#define MPC5XXX_XLBARB_CFG		(MPC5XXX_XLBARB + 0x40)#define MPC5XXX_XLBARB_MPRIEN	(MPC5XXX_XLBARB + 0x64)#define MPC5XXX_XLBARB_MPRIVAL	(MPC5XXX_XLBARB + 0x68)#endif/* GPIO registers */#define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)/* Standard GPIO registers (simple, output only and simple interrupt */#define MPC5XXX_GPIO_ENABLE     (MPC5XXX_GPIO + 0x0004)#define MPC5XXX_GPIO_ODE        (MPC5XXX_GPIO + 0x0008)#define MPC5XXX_GPIO_DIR        (MPC5XXX_GPIO + 0x000c)#define MPC5XXX_GPIO_DATA_O     (MPC5XXX_GPIO + 0x0010)#define MPC5XXX_GPIO_DATA_I     (MPC5XXX_GPIO + 0x0014)#define MPC5XXX_GPIO_OO_ENABLE  (MPC5XXX_GPIO + 0x0018)#define MPC5XXX_GPIO_OO_DATA    (MPC5XXX_GPIO + 0x001C)#define MPC5XXX_GPIO_SI_ENABLE  (MPC5XXX_GPIO + 0x0020)#define MPC5XXX_GPIO_SI_ODE     (MPC5XXX_GPIO + 0x0024)#define MPC5XXX_GPIO_SI_DIR     (MPC5XXX_GPIO + 0x0028)#define MPC5XXX_GPIO_SI_DATA    (MPC5XXX_GPIO + 0x002C)#define MPC5XXX_GPIO_SI_IEN     (MPC5XXX_GPIO + 0x0030)#define MPC5XXX_GPIO_SI_ITYPE   (MPC5XXX_GPIO + 0x0034)#define MPC5XXX_GPIO_SI_MEN     (MPC5XXX_GPIO + 0x0038)#define MPC5XXX_GPIO_SI_STATUS  (MPC5XXX_GPIO + 0x003C)/* WakeUp GPIO registers */#define MPC5XXX_WU_GPIO_ENABLE  (MPC5XXX_WU_GPIO + 0x0000)#define MPC5XXX_WU_GPIO_ODE     (MPC5XXX_WU_GPIO + 0x0004)#define MPC5XXX_WU_GPIO_DIR     (MPC5XXX_WU_GPIO + 0x0008)#define MPC5XXX_WU_GPIO_DATA    (MPC5XXX_WU_GPIO + 0x000c)/* PCI registers */#define MPC5XXX_PCI_CMD		(MPC5XXX_PCI + 0x04)#define MPC5XXX_PCI_CFG		(MPC5XXX_PCI + 0x0c)#define MPC5XXX_PCI_BAR0	(MPC5XXX_PCI + 0x10)#define MPC5XXX_PCI_BAR1	(MPC5XXX_PCI + 0x14)#if defined(CONFIG_MGT5100)#define MPC5XXX_PCI_CTRL	(MPC5XXX_PCI + 0x68)#define MPC5XXX_PCI_VALMSKR	(MPC5XXX_PCI + 0x6c)#define MPC5XXX_PCI_VALMSKW	(MPC5XXX_PCI + 0x70)#define MPC5XXX_PCI_SUBW1	(MPC5XXX_PCI + 0x74)#define MPC5XXX_PCI_SUBW2	(MPC5XXX_PCI + 0x78)#define MPC5XXX_PCI_WINCOMMAND	(MPC5XXX_PCI + 0x7c)#elif defined(CONFIG_MPC5200)#define MPC5XXX_PCI_GSCR	(MPC5XXX_PCI + 0x60)#define MPC5XXX_PCI_TBATR0	(MPC5XXX_PCI + 0x64)#define MPC5XXX_PCI_TBATR1	(MPC5XXX_PCI + 0x68)#define MPC5XXX_PCI_TCR		(MPC5XXX_PCI + 0x6c)#define MPC5XXX_PCI_IW0BTAR	(MPC5XXX_PCI + 0x70)#define MPC5XXX_PCI_IW1BTAR	(MPC5XXX_PCI + 0x74)#define MPC5XXX_PCI_IW2BTAR	(MPC5XXX_PCI + 0x78)#define MPC5XXX_PCI_IWCR	(MPC5XXX_PCI + 0x80)#define MPC5XXX_PCI_ICR		(MPC5XXX_PCI + 0x84)#define MPC5XXX_PCI_ISR		(MPC5XXX_PCI + 0x88)#define MPC5XXX_PCI_ARB		(MPC5XXX_PCI + 0x8c)#define MPC5XXX_PCI_CAR		(MPC5XXX_PCI + 0xf8)#endif/* Interrupt Controller registers */#define MPC5XXX_ICTL_PER_MASK	(MPC5XXX_ICTL + 0x0000)#define MPC5XXX_ICTL_PER_PRIO1	(MPC5XXX_ICTL + 0x0004)#define MPC5XXX_ICTL_PER_PRIO2	(MPC5XXX_ICTL + 0x0008)#define MPC5XXX_ICTL_PER_PRIO3	(MPC5XXX_ICTL + 0x000c)#define MPC5XXX_ICTL_EXT	(MPC5XXX_ICTL + 0x0010)#define MPC5XXX_ICTL_CRIT	(MPC5XXX_ICTL + 0x0014)#define MPC5XXX_ICTL_MAIN_PRIO1	(MPC5XXX_ICTL + 0x0018)#define MPC5XXX_ICTL_MAIN_PRIO2	(MPC5XXX_ICTL + 0x001c)#define MPC5XXX_ICTL_STS	(MPC5XXX_ICTL + 0x0024)#define MPC5XXX_ICTL_CRIT_STS	(MPC5XXX_ICTL + 0x0028)#define MPC5XXX_ICTL_MAIN_STS	(MPC5XXX_ICTL + 0x002c)#define MPC5XXX_ICTL_PER_STS	(MPC5XXX_ICTL + 0x0030)#define MPC5XXX_ICTL_BUS_STS	(MPC5XXX_ICTL + 0x0038)#define NR_IRQS			64/* IRQ mapping - these are our logical IRQ numbers */#define MPC5XXX_CRIT_IRQ_NUM	4#define MPC5XXX_MAIN_IRQ_NUM	17#define MPC5XXX_SDMA_IRQ_NUM	17#define MPC5XXX_PERP_IRQ_NUM	23#define MPC5XXX_CRIT_IRQ_BASE	1#define MPC5XXX_MAIN_IRQ_BASE	(MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)#define MPC5XXX_SDMA_IRQ_BASE	(MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)#define MPC5XXX_PERP_IRQ_BASE	(MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)#define MPC5XXX_IRQ0			(MPC5XXX_CRIT_IRQ_BASE + 0)#define MPC5XXX_SLICE_TIMER_0_IRQ	(MPC5XXX_CRIT_IRQ_BASE + 1)#define MPC5XXX_HI_INT_IRQ		(MPC5XXX_CRIT_IRQ_BASE + 2)#define MPC5XXX_CCS_IRQ			(MPC5XXX_CRIT_IRQ_BASE + 3)#define MPC5XXX_IRQ1			(MPC5XXX_MAIN_IRQ_BASE + 1)#define MPC5XXX_IRQ2			(MPC5XXX_MAIN_IRQ_BASE + 2)#define MPC5XXX_IRQ3			(MPC5XXX_MAIN_IRQ_BASE + 3)#define MPC5XXX_RTC_PINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 5)#define MPC5XXX_RTC_SINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 6)#define MPC5XXX_RTC_GPIO_STD_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 7)#define MPC5XXX_RTC_GPIO_WKUP_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 8)#define MPC5XXX_TMR0_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 9)#define MPC5XXX_TMR1_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 10)#define MPC5XXX_TMR2_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 11)#define MPC5XXX_TMR3_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 12)#define MPC5XXX_TMR4_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 13)#define MPC5XXX_TMR5_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 14)#define MPC5XXX_TMR6_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 15)#define MPC5XXX_TMR7_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 16)#define MPC5XXX_SDMA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 0)#define MPC5XXX_PSC1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 1)#define MPC5XXX_PSC2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 2)#define MPC5XXX_PSC3_IRQ		(MPC5XXX_PERP_IRQ_BASE + 3)#define MPC5XXX_PSC6_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)#define MPC5XXX_IRDA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)#define MPC5XXX_FEC_IRQ			(MPC5XXX_PERP_IRQ_BASE + 5)#define MPC5XXX_USB_IRQ			(MPC5XXX_PERP_IRQ_BASE + 6)#define MPC5XXX_ATA_IRQ			(MPC5XXX_PERP_IRQ_BASE + 7)#define MPC5XXX_PCI_CNTRL_IRQ		(MPC5XXX_PERP_IRQ_BASE + 8)#define MPC5XXX_PCI_SCIRX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 9)#define MPC5XXX_PCI_SCITX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 10)#define MPC5XXX_PSC4_IRQ		(MPC5XXX_PERP_IRQ_BASE + 11)#define MPC5XXX_PSC5_IRQ		(MPC5XXX_PERP_IRQ_BASE + 12)#define MPC5XXX_SPI_MODF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 13)#define MPC5XXX_SPI_SPIF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 14)#define MPC5XXX_I2C1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 15)#define MPC5XXX_I2C2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 16)#define MPC5XXX_MSCAN1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 17)#define MPC5XXX_MSCAN2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 18)#define MPC5XXX_IR_RX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 19)#define MPC5XXX_IR_TX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 20)#define MPC5XXX_XLB_ARB_IRQ		(MPC5XXX_PERP_IRQ_BASE + 21)#define MPC5XXX_BDLC_IRQ		(MPC5XXX_PERP_IRQ_BASE + 22)/* General Purpose Timers registers */#define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)#define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)#define MPC5XXX_GPT0_STATUS		(MPC5XXX_GPT + 0x0C)#define MPC5XXX_GPT1_ENABLE		(MPC5XXX_GPT + 0x10)#define MPC5XXX_GPT1_COUNTER		(MPC5XXX_GPT + 0x14)#define MPC5XXX_GPT1_STATUS		(MPC5XXX_GPT + 0x1C)#define MPC5XXX_GPT2_ENABLE		(MPC5XXX_GPT + 0x20)#define MPC5XXX_GPT2_COUNTER		(MPC5XXX_GPT + 0x24)#define MPC5XXX_GPT2_STATUS		(MPC5XXX_GPT + 0x2C)#define MPC5XXX_GPT3_ENABLE		(MPC5XXX_GPT + 0x30)#define MPC5XXX_GPT3_COUNTER		(MPC5XXX_GPT + 0x34)#define MPC5XXX_GPT3_STATUS		(MPC5XXX_GPT + 0x3C)#define MPC5XXX_GPT4_ENABLE		(MPC5XXX_GPT + 0x40)#define MPC5XXX_GPT4_COUNTER		(MPC5XXX_GPT + 0x44)#define MPC5XXX_GPT4_STATUS		(MPC5XXX_GPT + 0x4C)#define MPC5XXX_GPT5_ENABLE		(MPC5XXX_GPT + 0x50)#define MPC5XXX_GPT5_STATUS		(MPC5XXX_GPT + 0x5C)#define MPC5XXX_GPT5_COUNTER		(MPC5XXX_GPT + 0x54)#define MPC5XXX_GPT6_ENABLE		(MPC5XXX_GPT + 0x60)#define MPC5XXX_GPT6_COUNTER		(MPC5XXX_GPT + 0x64)#define MPC5XXX_GPT6_STATUS		(MPC5XXX_GPT + 0x6C)#define MPC5XXX_GPT7_ENABLE		(MPC5XXX_GPT + 0x70)#define MPC5XXX_GPT7_COUNTER		(MPC5XXX_GPT + 0x74)#define MPC5XXX_GPT7_STATUS		(MPC5XXX_GPT + 0x7C)#define MPC5XXX_GPT_GPIO_PIN(status)	((0x00000100 & (status)) >> 8)#define MPC5XXX_GPT7_PWMCFG		(MPC5XXX_GPT + 0x78)/* ATA registers */#define MPC5XXX_ATA_HOST_CONFIG         (MPC5XXX_ATA + 0x0000)#define MPC5XXX_ATA_PIO1                (MPC5XXX_ATA + 0x0008)#define MPC5XXX_ATA_PIO2                (MPC5XXX_ATA + 0x000C)#define MPC5XXX_ATA_SHARE_COUNT         (MPC5XXX_ATA + 0x002C)/* I2Cn control register bits */#define I2C_EN		0x80#define I2C_IEN		0x40#define I2C_STA		0x20#define I2C_TX		0x10#define I2C_TXAK	0x08#define I2C_RSTA	0x04#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)/* I2Cn status register bits */#define I2C_CF		0x80#define I2C_AAS		0x40#define I2C_BB		0x20#define I2C_AL		0x10#define I2C_SRW		0x04#define I2C_IF		0x02#define I2C_RXAK	0x01/* Programmable Serial Controller (PSC) status register bits */#define PSC_SR_CDE		0x0080#define PSC_SR_RXRDY		0x0100#define PSC_SR_RXFULL		0x0200#define PSC_SR_TXRDY		0x0400#define PSC_SR_TXEMP		0x0800#define PSC_SR_OE		0x1000#define PSC_SR_PE		0x2000#define PSC_SR_FE		0x4000#define PSC_SR_RB		0x8000/* PSC Command values */#define PSC_RX_ENABLE		0x0001#define PSC_RX_DISABLE		0x0002#define PSC_TX_ENABLE		0x0004#define PSC_TX_DISABLE		0x0008#define PSC_SEL_MODE_REG_1	0x0010#define PSC_RST_RX		0x0020#define PSC_RST_TX		0x0030#define PSC_RST_ERR_STAT	0x0040#define PSC_RST_BRK_CHG_INT	0x0050#define PSC_START_BRK		0x0060#define PSC_STOP_BRK		0x0070/* PSC Rx FIFO status bits */#define PSC_RX_FIFO_ERR		0x0040#define PSC_RX_FIFO_UF		0x0020#define PSC_RX_FIFO_OF		0x0010#define PSC_RX_FIFO_FR		0x0008#define PSC_RX_FIFO_FULL	0x0004#define PSC_RX_FIFO_ALARM	0x0002#define PSC_RX_FIFO_EMPTY	0x0001/* PSC interrupt mask bits */#define PSC_IMR_TXRDY		0x0100#define PSC_IMR_RXRDY		0x0200#define PSC_IMR_DB		0x0400#define PSC_IMR_IPC		0x8000/* PSC input port change bits */#define PSC_IPCR_CTS		0x01
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