mpc8220.h

u-boot-1.1.6 源码包

#define CFG1_WLATENCY_SHIFT	    4

#define CFG1_SRD2RWP(value)	    ((value)<<CFG1_SRD2RWP_SHIFT)
#define CFG1_SWT2RWP(value)	    ((value)<<CFG1_SWT2RWP_SHIFT)
#define CFG1_RLATENCY(value)	    ((value)<<CFG1_RLATENCY_SHIFT)
#define CFG1_ACT2WR(value)	    ((value)<<CFG1_ACT2WR_SHIFT)
#define CFG1_PRE2ACT(value)	    ((value)<<CFG1_PRE2ACT_SHIFT)
#define CFG1_REF2ACT(value)	    ((value)<<CFG1_REF2ACT_SHIFT)
#define CFG1_WLATENCY(value)	    ((value)<<CFG1_WLATENCY_SHIFT)

/* Field definitions for config register 2 */
#define CFG2_BRD2RP_SHIFT	    28
#define CFG2_BWT2RWP_SHIFT	    24
#define CFG2_BRD2WT_SHIFT	    20
#define CFG2_BURSTLEN_SHIFT	    16

#define CFG2_BRD2RP(value)	    ((value)<<CFG2_BRD2RP_SHIFT)
#define CFG2_BWT2RWP(value)	    ((value)<<CFG2_BWT2RWP_SHIFT)
#define CFG2_BRD2WT(value)	    ((value)<<CFG2_BRD2WT_SHIFT)
#define CFG2_BURSTLEN(value)	    ((value)<<CFG2_BURSTLEN_SHIFT)

/* Field definitions for the mode/extended mode register - mode
 * register access
 */
#define MODE_REG_SHIFT		    30
#define MODE_OPMODE_SHIFT	    25
#define MODE_CL_SHIFT		    22
#define MODE_BT_SHIFT		    21
#define MODE_BURSTLEN_SHIFT	    18
#define MODE_CMD_SHIFT		    16

#define MODE_MODE		    0
#define MODE_OPMODE(value)	    ((value)<<MODE_OPMODE_SHIFT)
#define MODE_CL(value)		    ((value)<<MODE_CL_SHIFT)
#define MODE_BT_INTERLEAVED	    (1<<MODE_BT_SHIFT)
#define MODE_BT_SEQUENTIAL	    (0<<MODE_BT_SHIFT)
#define MODE_BURSTLEN(value)	    ((value)<<MODE_BURSTLEN_SHIFT)
#define MODE_CMD		    (1<<MODE_CMD_SHIFT)

#define MODE_BURSTLEN_8		    3
#define MODE_BURSTLEN_4		    2
#define MODE_BURSTLEN_2		    1

#define MODE_CL_2		    2
#define MODE_CL_2p5		    6
#define MODE_OPMODE_NORMAL	    0
#define MODE_OPMODE_RESETDLL	    2


/* Field definitions for the mode/extended mode register - extended
 * mode register access
 */
#define MODE_X_DLL_SHIFT	    18 /* DLL enable/disable */
#define MODE_X_DS_SHIFT		    19 /* Drive strength normal/reduced */
#define MODE_X_QFC_SHIFT	    20 /* QFC function (whatever that is) */
#define MODE_X_OPMODE_SHIFT	    21

#define MODE_EXTENDED		    (1<<MODE_REG_SHIFT)
#define MODE_X_DLL_ENABLE	    0
#define MODE_X_DLL_DISABLE	    (1<<MODE_X_DLL_SHIFT)
#define MODE_X_DS_NORMAL	    0
#define MODE_X_DS_REDUCED	    (1<<MODE_X_DS_SHIFT)
#define MODE_X_QFC_DISABLED	    0
#define MODE_X_OPMODE(value)	    ((value)<<MODE_X_OPMODE_SHIFT)

#ifndef __ASSEMBLY__
/*
 * DMA control/status registers.
 */
struct mpc8220_dma {
    u32 taskBar;	/* DMA + 0x00 */
    u32 currentPointer; /* DMA + 0x04 */
    u32 endPointer;	/* DMA + 0x08 */
    u32 variablePointer;/* DMA + 0x0c */

    u8 IntVect1;	/* DMA + 0x10 */
    u8 IntVect2;	/* DMA + 0x11 */
    u16 PtdCntrl;	/* DMA + 0x12 */

    u32 IntPend;	/* DMA + 0x14 */
    u32 IntMask;	/* DMA + 0x18 */

    u16 tcr_0;		/* DMA + 0x1c */
    u16 tcr_1;		/* DMA + 0x1e */
    u16 tcr_2;		/* DMA + 0x20 */
    u16 tcr_3;		/* DMA + 0x22 */
    u16 tcr_4;		/* DMA + 0x24 */
    u16 tcr_5;		/* DMA + 0x26 */
    u16 tcr_6;		/* DMA + 0x28 */
    u16 tcr_7;		/* DMA + 0x2a */
    u16 tcr_8;		/* DMA + 0x2c */
    u16 tcr_9;		/* DMA + 0x2e */
    u16 tcr_a;		/* DMA + 0x30 */
    u16 tcr_b;		/* DMA + 0x32 */
    u16 tcr_c;		/* DMA + 0x34 */
    u16 tcr_d;		/* DMA + 0x36 */
    u16 tcr_e;		/* DMA + 0x38 */
    u16 tcr_f;		/* DMA + 0x3a */

    u8 IPR0;		/* DMA + 0x3c */
    u8 IPR1;		/* DMA + 0x3d */
    u8 IPR2;		/* DMA + 0x3e */
    u8 IPR3;		/* DMA + 0x3f */
    u8 IPR4;		/* DMA + 0x40 */
    u8 IPR5;		/* DMA + 0x41 */
    u8 IPR6;		/* DMA + 0x42 */
    u8 IPR7;		/* DMA + 0x43 */
    u8 IPR8;		/* DMA + 0x44 */
    u8 IPR9;		/* DMA + 0x45 */
    u8 IPR10;		/* DMA + 0x46 */
    u8 IPR11;		/* DMA + 0x47 */
    u8 IPR12;		/* DMA + 0x48 */
    u8 IPR13;		/* DMA + 0x49 */
    u8 IPR14;		/* DMA + 0x4a */
    u8 IPR15;		/* DMA + 0x4b */
    u8 IPR16;		/* DMA + 0x4c */
    u8 IPR17;		/* DMA + 0x4d */
    u8 IPR18;		/* DMA + 0x4e */
    u8 IPR19;		/* DMA + 0x4f */
    u8 IPR20;		/* DMA + 0x50 */
    u8 IPR21;		/* DMA + 0x51 */
    u8 IPR22;		/* DMA + 0x52 */
    u8 IPR23;		/* DMA + 0x53 */
    u8 IPR24;		/* DMA + 0x54 */
    u8 IPR25;		/* DMA + 0x55 */
    u8 IPR26;		/* DMA + 0x56 */
    u8 IPR27;		/* DMA + 0x57 */
    u8 IPR28;		/* DMA + 0x58 */
    u8 IPR29;		/* DMA + 0x59 */
    u8 IPR30;		/* DMA + 0x5a */
    u8 IPR31;		/* DMA + 0x5b */

    u32 res1;		/* DMA + 0x5c */
    u32 res2;		/* DMA + 0x60 */
    u32 res3;		/* DMA + 0x64 */
    u32 MDEDebug;	/* DMA + 0x68 */
    u32 ADSDebug;	/* DMA + 0x6c */
    u32 Value1;		/* DMA + 0x70 */
    u32 Value2;		/* DMA + 0x74 */
    u32 Control;	/* DMA + 0x78 */
    u32 Status;		/* DMA + 0x7c */
    u32 EU00;		/* DMA + 0x80 */
    u32 EU01;		/* DMA + 0x84 */
    u32 EU02;		/* DMA + 0x88 */
    u32 EU03;		/* DMA + 0x8c */
    u32 EU04;		/* DMA + 0x90 */
    u32 EU05;		/* DMA + 0x94 */
    u32 EU06;		/* DMA + 0x98 */
    u32 EU07;		/* DMA + 0x9c */
    u32 EU10;		/* DMA + 0xa0 */
    u32 EU11;		/* DMA + 0xa4 */
    u32 EU12;		/* DMA + 0xa8 */
    u32 EU13;		/* DMA + 0xac */
    u32 EU14;		/* DMA + 0xb0 */
    u32 EU15;		/* DMA + 0xb4 */
    u32 EU16;		/* DMA + 0xb8 */
    u32 EU17;		/* DMA + 0xbc */
    u32 EU20;		/* DMA + 0xc0 */
    u32 EU21;		/* DMA + 0xc4 */
    u32 EU22;		/* DMA + 0xc8 */
    u32 EU23;		/* DMA + 0xcc */
    u32 EU24;		/* DMA + 0xd0 */
    u32 EU25;		/* DMA + 0xd4 */
    u32 EU26;		/* DMA + 0xd8 */
    u32 EU27;		/* DMA + 0xdc */
    u32 EU30;		/* DMA + 0xe0 */
    u32 EU31;		/* DMA + 0xe4 */
    u32 EU32;		/* DMA + 0xe8 */
    u32 EU33;		/* DMA + 0xec */
    u32 EU34;		/* DMA + 0xf0 */
    u32 EU35;		/* DMA + 0xf4 */
    u32 EU36;		/* DMA + 0xf8 */
    u32 EU37;		/* DMA + 0xfc */
};

/*
 * PCI Header Registers
 */
typedef struct mpc8220_xcpci {
	u32	dev_ven_id;		/* 0xb00 - device/vendor ID */
	u32	stat_cmd_reg;		/* 0xb04 - status command register */
	u32	class_code_rev_id;	/* 0xb08 - class code / revision ID */
	u32	bist_htyp_lat_cshl;	/* 0xb0c - BIST/HeaderType/Latency/cache line */
	u32	base0;			/* 0xb10 - base address 0 */
	u32	base1;			/* 0xb14 - base address 1 */
	u32	reserved1[4];		/* 0xb18->0xd27 - base address 2 - 5 */
	u32	cis;			/* 0xb28 - cardBus CIS pointer */
	u32	sub_sys_ven_id;		/* 0xb2c - sub system ID/ subsystem vendor ID */
	u32	reserved2;		/* 0xb30 - expansion ROM base address */
	u32	reserved3;		/* 0xb00 - reserved */
	u32	reserved4;		/* 0xb00 - reserved */
	u32	mlat_mgnt_ipl;		/* 0xb3c - MaxLat/MinGnt/ int pin/int line */
	u32	reserved5[8];
	/* MPC8220 specific - not accessible in PCI header space externally */
	u32	glb_stat_ctl;		/* 0xb60 - Global Status Control */
	u32	target_bar0;		/* 0xb64 - Target Base Address 0 */
	u32	target_bar1;		/* 0xb68 - Target Base Address 1 */
	u32	target_ctrl;		/* 0xb6c - Target Control */
	u32	init_win0;		/* 0xb70 - Initiator Window 0 Base/Translation */
	u32	init_win1;		/* 0xb74 - Initiator Window 1 Base/Translation */
	u32	init_win2;		/* 0xb78 - Initiator Window 2 Base/Translation */
	u32	reserved6;		/* 0xb7c - reserved  */
	u32	init_win_cfg;		/* 0xb80 */
	u32	init_ctrl;		/* 0xb84 */
	u32	init_stat;		/* 0xb88 */
	u32	reserved7[27];
	u32	cfg_adr;		/* 0xbf8 */
	u32	reserved8;
} mpc8220_xcpci_t;

/* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB,
   reg1 - 1GB */
#define PCI_BASE_ADDR_REG0			0x40000000
#define PCI_BASE_ADDR_REG1			(CFG_SDRAM_BASE)
#define PCI_TARGET_BASE_ADDR_REG0		(CFG_MBAR)
#define PCI_TARGET_BASE_ADDR_REG1		(CFG_SDRAM_BASE)
#define PCI_TARGET_BASE_ADDR_EN			1<<0


/* PCI Global Status/Control Register (PCIGSCR) */
#define PCI_GLB_STAT_CTRL_PE_SHIFT		29
#define PCI_GLB_STAT_CTRL_SE_SHIFT		28
#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT	24
#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK	0x7
#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT	16
#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK	0x7
#define PCI_GLB_STAT_CTRL_PEE_SHIFT		13
#define PCI_GLB_STAT_CTRL_SEE_SHIFT		12
#define PCI_GLB_STAT_CTRL_PR_SHIFT		0

#define PCI_GLB_STAT_CTRL_PE			(1<<PCI_GLB_STAT_CTRL_PE_SHIFT)
#define PCI_GLB_STAT_CTRL_SE			(1<<PCI_GLB_STAT_CTRL_SE_SHIFT)
#define PCI_GLB_STAT_CTRL_PEE			(1<<PCI_GLB_STAT_CTRL_PEE_SHIFT)
#define PCI_GLB_STAT_CTRL_SEE			(1<<PCI_GLB_STAT_CTRL_SEE_SHIFT)
#define PCI_GLB_STAT_CTRL_PR			(1<<PCI_GLB_STAT_CTRL_PR_SHIFT)

/* PCI Target Control Register (PCITCR) */
#define PCI_TARGET_CTRL_LD_SHIFT		24
#define PCI_TARGET_CTRL_P_SHIFT			16

#define PCI_TARGET_CTRL_LD			(1<<PCI_TARGET_CTRL_LD_SHIFT)
#define PCI_TARGET_CTRL_P			(1<<PCI_TARGET_CTRL_P_SHIFT)

/* PCI Initiator Window Configuration Register (PCIIWCR) */
#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT	27
#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_SHIFT	25
#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_MASK	0x3
#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT	24
#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT	19
#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_SHIFT	17
#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_MASK	0x3
#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT	16
#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT	11
#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_SHIFT	9
#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_MASK	0x3
#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT	8

#define PCI_INIT_WIN_CFG_WIN_MEM_READ		0x0
#define PCI_INIT_WIN_CFG_WIN_MEM_READ_LINE	0x1
#define PCI_INIT_WIN_CFG_WIN_MEM_READ_MULTIPLE	0x2

#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT)
#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT)
#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT)
#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT)
#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT)
#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT)

/* PCI Initiator Control Register (PCIICR) */
#define PCI_INIT_CTRL_REE_SHIFT			26
#define PCI_INIT_CTRL_IAE_SHIFT			25
#define PCI_INIT_CTRL_TAE_SHIFT			24
#define PCI_INIT_CTRL_MAX_RETRIES_SHIFT		0
#define PCI_INIT_CTRL_MAX_RETRIES_MASK		0xff

#define PCI_INIT_CTRL_REE			(1<<PCI_INIT_CTRL_REE_SHIFT)
#define PCI_INIT_CTRL_IAE			(1<<PCI_INIT_CTRL_IAE_SHIFT)
#define PCI_INIT_CTRL_TAE			(1<<PCI_INIT_CTRL_TAE_SHIFT)

/* PCI Status/Command Register (PCISCR) - PCI Dword 1 */
#define PCI_STAT_CMD_PE_SHIFT			31
#define PCI_STAT_CMD_SE_SHIFT			30
#define PCI_STAT_CMD_MA_SHIFT			29
#define PCI_STAT_CMD_TR_SHIFT			28
#define PCI_STAT_CMD_TS_SHIFT			27
#define PCI_STAT_CMD_DT_SHIFT			25
#define PCI_STAT_CMD_DT_MASK			0x3
#define PCI_STAT_CMD_DP_SHIFT			24
#define PCI_STAT_CMD_FC_SHIFT			23
#define PCI_STAT_CMD_R_SHIFT			22
#define PCI_STAT_CMD_66M_SHIFT			21
#define PCI_STAT_CMD_C_SHIFT			20
#define PCI_STAT_CMD_F_SHIFT			9
#define PCI_STAT_CMD_S_SHIFT			8
#define PCI_STAT_CMD_ST_SHIFT			7
#define PCI_STAT_CMD_PER_SHIFT			6
#define PCI_STAT_CMD_V_SHIFT			5
#define PCI_STAT_CMD_MW_SHIFT			4
#define PCI_STAT_CMD_SP_SHIFT			3
#define PCI_STAT_CMD_B_SHIFT			2
#define PCI_STAT_CMD_M_SHIFT			1
#define PCI_STAT_CMD_IO_SHIFT			0

#define PCI_STAT_CMD_PE			(1<<PCI_STAT_CMD_PE_SHIFT)
#define PCI_STAT_CMD_SE			(1<<PCI_STAT_CMD_SE_SHIFT)
#define PCI_STAT_CMD_MA			(1<<PCI_STAT_CMD_MA_SHIFT)
#define PCI_STAT_CMD_TR			(1<<PCI_STAT_CMD_TR_SHIFT)
#define PCI_STAT_CMD_TS			(1<<PCI_STAT_CMD_TS_SHIFT)
#define PCI_STAT_CMD_DP			(1<<PCI_STAT_CMD_DP_SHIFT)
#define PCI_STAT_CMD_FC			(1<<PCI_STAT_CMD_FC_SHIFT)
#define PCI_STAT_CMD_R				(1<<PCI_STAT_CMD_R_SHIFT)
#define PCI_STAT_CMD_66M			(1<<PCI_STAT_CMD_66M_SHIFT)
#define PCI_STAT_CMD_C				(1<<PCI_STAT_CMD_C_SHIFT)
#define PCI_STAT_CMD_F				(1<<PCI_STAT_CMD_F_SHIFT)
#define PCI_STAT_CMD_S				(1<<PCI_STAT_CMD_S_SHIFT)
#define PCI_STAT_CMD_ST			(1<<PCI_STAT_CMD_ST_SHIFT)
#define PCI_STAT_CMD_PER			(1<<PCI_STAT_CMD_PER_SHIFT)
#define PCI_STAT_CMD_V				(1<<PCI_STAT_CMD_V_SHIFT)
#define PCI_STAT_CMD_MW			(1<<PCI_STAT_CMD_MW_SHIFT)
#define PCI_STAT_CMD_SP			(1<<PCI_STAT_CMD_SP_SHIFT)
#define PCI_STAT_CMD_B				(1<<PCI_STAT_CMD_B_SHIFT)
#define PCI_STAT_CMD_M				(1<<PCI_STAT_CMD_M_SHIFT)
#define PCI_STAT_CMD_IO			(1<<PCI_STAT_CMD_IO_SHIFT)

/* PCI Configuration 1 Register (PCICR1) - PCI Dword 3 */
#define PCI_CFG1_HT_SHIFT			16
#define PCI_CFG1_HT_MASK			0xff
#define PCI_CFG1_LT_SHIFT			8
#define PCI_CFG1_LT_MASK			0xff
#define PCI_CFG1_CLS_SHIFT			0
#define PCI_CFG1_CLS_MASK			0xf

/* function prototypes */
void loadtask(int basetask, int tasks);
u32 dramSetup(void);

#if defined(CONFIG_PSC_CONSOLE)
int psc_serial_init (void);
void psc_serial_putc(const char c);
void psc_serial_puts (const char *s);
int psc_serial_getc(void);
int psc_serial_tstc(void);
void psc_serial_setbrg(void);
#endif

#if defined (CONFIG_EXTUART_CONSOLE)
int ext_serial_init (void);
void ext_serial_putc(const char c);
void ext_serial_puts (const char *s);
int ext_serial_getc(void);
int ext_serial_tstc(void);
void ext_serial_setbrg(void);
#endif

#endif /* __ASSEMBLY__ */

#endif /* __MPC8220_H__ */