catcenter.h

u-boot-1.1.6 源码包

/*
 * ueberarbeitet durch Christoph Seyfert
 *
 * (C) Copyright 2004-2005 DENX Software Engineering,
 *     Wolfgang Grandegger <[e-mail]>
 * (C) Copyright 2003
 *     DAVE Srl
 *
 * http://www.dave-tech.it
 * http://www.wawnet.biz
 * mailto:[e-mail]
 *
 * Credits: Stefan Roese, Wolfgang Denk
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
#define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
#define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
#endif

/* Only one of the following two symbols must be defined (default is 25 MHz)
 * CONFIG_PPCHAMELEON_CLK_25
 * CONFIG_PPCHAMELEON_CLK_33
 */
#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
#define CONFIG_PPCHAMELEON_CLK_25
#endif

#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
#error "* Two external frequencies (SysClk) are defined! *"
#endif

#undef CONFIG_PPCHAMELEON_SMI712

/*
 * Debug stuff
 */
#undef	__DEBUG_START_FROM_SRAM__
#define __DISABLE_MACHINE_EXCEPTION__

#ifdef __DEBUG_START_FROM_SRAM__
#define CFG_DUMMY_FLASH_SIZE		1024*1024*4
#endif

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

#ifdef CONFIG_PPCHAMELEON_CLK_25
# define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll   */
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
#else
# error "* External frequency (SysClk) not defined! *"
#endif

#define CONFIG_UART1_CONSOLE	1	/* Use second UART		*/
#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_VERSION_VARIABLE	1	/* add version variable		*/
#define CONFIG_IDENT_STRING	"1"

#undef	CONFIG_BOOTARGS

/* Ethernet stuff */
#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
#define CONFIG_ETHADDR	00:50:C2:1E:AF:FE
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/


#undef CONFIG_EXT_PHY
#define CONFIG_NET_MULTI	1

#define CONFIG_MII		1	/* MII PHY management		*/
#ifndef	 CONFIG_EXT_PHY
#define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
#define CONFIG_PHY1_ADDR	16	/* EMAC1 PHY address		*/
#else
#define CONFIG_PHY_ADDR		2	/* PHY address			*/
#endif
#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_ELF	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_JFFS2	| \
				CFG_CMD_MII	| \
				CFG_CMD_NAND	| \
				CFG_CMD_NFS	| \
				CFG_CMD_SNTP	)

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/

#define	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
#define CFG_BASE_BAUD		691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * NAND-FLASH stuff
 *-----------------------------------------------------------------------
 */
#define CFG_NAND0_BASE 0xFF400000
#define CFG_NAND1_BASE 0xFF000000
#define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE }
#define NAND_BIG_DELAY_US	25

/* For CATcenter there is only NAND on the module */
#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
#define SECTORSIZE 512
#define NAND_NO_RB

#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN	0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1

#define CFG_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
#define CFG_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
#define CFG_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */

#define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
#define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
#define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */


#define MACRO_NAND_DISABLE_CE(nandptr) do \
{ \
	switch((unsigned long)nandptr) \
	{ \
	    case CFG_NAND0_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
		break; \
	    case CFG_NAND1_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
		break; \
	} \
} while(0)

#define MACRO_NAND_ENABLE_CE(nandptr) do \
{ \
	switch((unsigned long)nandptr) \
	{ \
	    case CFG_NAND0_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
		break; \
	    case CFG_NAND1_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
		break; \
	} \
} while(0)

#define MACRO_NAND_CTL_CLRALE(nandptr) do \
{ \
	switch((unsigned long)nandptr) \
	{ \
	    case CFG_NAND0_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
		break; \
	    case CFG_NAND1_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
		break; \
	} \
} while(0)

#define MACRO_NAND_CTL_SETALE(nandptr) do \
{ \
	switch((unsigned long)nandptr) \
	{ \
	    case CFG_NAND0_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
		break; \
	    case CFG_NAND1_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
		break; \
	} \
} while(0)

#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
{ \
	switch((unsigned long)nandptr) \
	{ \
	    case CFG_NAND0_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
		break; \
	    case CFG_NAND1_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
		break; \
	} \
} while(0)

#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
	switch((unsigned long)nandptr) { \
	case CFG_NAND0_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
		break; \
	case CFG_NAND1_BASE: \
		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
		break; \
	} \
} while(0)

#ifdef NAND_NO_RB
/* constant delay (see also tR in the datasheet) */
#define NAND_WAIT_READY(nand) do { \
	udelay(12); \
} while (0)
#else
/* use the R/B pin */
/* TBD */
#endif

#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#if 0	/* No PCI on CATcenter */
#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_FORCE	 /* select pci host function	 */
#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/

#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
#endif	/* No PCI */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFC0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
#define CFG_ENV_ADDR		0xFFFF8000	/* environment starts at the first small sector */
#define CFG_ENV_SECT_SIZE	0x2000	/* 8196 bytes may be used for env vars*/
#define CFG_ENV_ADDR_REDUND	0xFFFFA000
#define CFG_ENV_SIZE_REDUND	0x2000

#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */