lwmon.h

u-boot-1.1.6 源码包

/* Put environment in flash which is much faster to boot than using the EEPROM	*/
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR	    0x40040000	/* Address    of Environment Sector	*/
#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment		*/
#define CFG_ENV_SECT_SIZE	0x40000 /* we have BIG sectors only :-(		*/

/*-----------------------------------------------------------------------
 * I2C/EEPROM Configuration
 */

#define CFG_I2C_AUDIO_ADDR	0x28	/* Audio volume control			*/
#define CFG_I2C_SYSMON_ADDR	0x2E	/* LM87 System Monitor			*/
#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
#define CFG_I2C_POWER_A_ADDR	0x52	/* PCMCIA/USB power switch, channel A	*/
#define CFG_I2C_POWER_B_ADDR	0x53	/* PCMCIA/USB power switch, channel B	*/
#define CFG_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard			*/
#define CFG_I2C_PICIO_ADDR	0x57	/* PIC IO Expander			*/

#undef	CONFIG_USE_FRAM			/* Use FRAM instead of EEPROM	*/

#ifdef CONFIG_USE_FRAM	/* use FRAM */
#define CFG_I2C_EEPROM_ADDR	0x55	/* FRAM FM24CL64		*/
#define CFG_I2C_EEPROM_ADDR_LEN	2
#else			/* use EEPROM */
#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
#define CFG_I2C_EEPROM_ADDR_LEN	1
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
#endif	/* CONFIG_USE_FRAM */
#define CFG_EEPROM_PAGE_WRITE_BITS	4

/* List of I2C addresses to be verified by POST */
#ifdef CONFIG_USE_FRAM
#define I2C_ADDR_LIST	{  /*	CFG_I2C_AUDIO_ADDR, */	\
				CFG_I2C_SYSMON_ADDR,	\
				CFG_I2C_RTC_ADDR,	\
				CFG_I2C_POWER_A_ADDR,	\
				CFG_I2C_POWER_B_ADDR,	\
				CFG_I2C_KEYBD_ADDR,	\
				CFG_I2C_PICIO_ADDR,	\
				CFG_I2C_EEPROM_ADDR,	\
			}
#else	/* Use EEPROM - which show up on 8 consequtive addresses */
#define I2C_ADDR_LIST	{  /*	CFG_I2C_AUDIO_ADDR, */	\
				CFG_I2C_SYSMON_ADDR,	\
				CFG_I2C_RTC_ADDR,	\
				CFG_I2C_POWER_A_ADDR,	\
				CFG_I2C_POWER_B_ADDR,	\
				CFG_I2C_KEYBD_ADDR,	\
				CFG_I2C_PICIO_ADDR,	\
				CFG_I2C_EEPROM_ADDR+0,	\
				CFG_I2C_EEPROM_ADDR+1,	\
				CFG_I2C_EEPROM_ADDR+2,	\
				CFG_I2C_EEPROM_ADDR+3,	\
				CFG_I2C_EEPROM_ADDR+4,	\
				CFG_I2C_EEPROM_ADDR+5,	\
				CFG_I2C_EEPROM_ADDR+6,	\
				CFG_I2C_EEPROM_ADDR+7,	\
			}
#endif	/* CONFIG_USE_FRAM */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if 0 && defined(CONFIG_WATCHDOG)	/* LWMON uses external MAX706TESA WD */
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
/* EARB, DBGC and DBPC are initialised by the HCW */
/* => 0x000000C0 */
#define CFG_SIUMCR	(SIUMCR_GB5E)
/*#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit, set PLL multiplication factor !
 */
/* 0x00405000 */
#define CFG_PLPRCR_MF	4	/* (4+1) * 13.2 = 66 MHz Clock */
#define CFG_PLPRCR							\
		(	(CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\
			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
			PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/	\
		)

#define CONFIG_8xx_GCLK_FREQ	((CFG_PLPRCR_MF+1)*13200000)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
/* 0x01800000 */
#define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
			 SCCR_EBDF00 |	 SCCR_DFSYNC00 |	\
			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
			 SCCR_DFNH000	|   SCCR_DFLCD100 |	\
			 SCCR_DFALCD01)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/* 0x00C3 => 0x0003 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)


/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration Register		19-4
 *-----------------------------------------------------------------------
 */
#define CFG_RCCR 0x0000

/*-----------------------------------------------------------------------
 * RMDS - RISC Microcode Development Support Control Register
 *-----------------------------------------------------------------------
 */
#define CFG_RMDS 0

/*-----------------------------------------------------------------------
 *
 * Interrupt Levels
 *-----------------------------------------------------------------------
 */
#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0x50000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0x54000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0x58000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0x5C000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0100

#define CONFIG_SUPPORT_VFAT		/* enable VFAT support */

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x41000000	/* FLASH bank #1	*/

/* used to re-map FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0xFF000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xFF000000	/* OR addr mask */

/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0	*/
#define CFG_OR_TIMING_FLASH	(OR_SCY_8_CLK)

#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
				CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
				CFG_OR_TIMING_FLASH)
/* 16 bit, bank valid */
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )

#define CFG_OR1_REMAP	CFG_OR0_REMAP
#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )

/*
 * BR3/OR3: SDRAM
 *
 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 */
#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
#define SDRAM_PRELIM_OR_AM	0xF0000000	/* map 256 MB (>SDRAM_MAX_SIZE!) */
#define SDRAM_TIMING		OR_SCY_0_CLK	/* SDRAM-Timing */

#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB SDRAM */

#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * BR5/OR5: Touch Panel
 *
 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 */
#define TOUCHPNL_BASE		0x20000000
#define TOUCHPNL_OR_AM		0xFFFF8000
#define TOUCHPNL_TIMING		OR_SCY_0_CLK

#define CFG_OR5_PRELIM	(TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
			 TOUCHPNL_TIMING )
#define CFG_BR5_PRELIM	((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )

#define	CFG_MEMORY_75
#undef	CFG_MEMORY_7E
#undef	CFG_MEMORY_8E

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CFG_MPTPR	0x200

/*
 * MAMR settings for SDRAM
 */

#define CFG_MAMR_8COL	0x80802114
#define CFG_MAMR_9COL	0x80904114

/*
 * MAR setting for SDRAM
 */
#define CFG_MAR		0x00000088

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */