adnpesc1.h

u-boot-1.1.6 源码包

/*
 * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
 * Stephan Linz <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/***********************************************************************
 * Include the whole NIOS CPU configuration.
 *
 * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
 *
 ***********************************************************************/

#if	defined(CONFIG_NIOS_BASE_32)
#include <configs/ADNPESC1_base_32.h>
#else
#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
#endif

/*------------------------------------------------------------------------
 * BOARD/CPU -- TOP-LEVEL
 *----------------------------------------------------------------------*/
#define CONFIG_NIOS		1		/* NIOS-32 core		*/
#define	CONFIG_ADNPESC1		1		/* SSV ADNP/ESC1 board	*/
#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
#define	CFG_HZ			1000		/* 1 msec time tick	*/
#undef  CFG_CLKS_IN_HZ
#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/

/*------------------------------------------------------------------------
 * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)

#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE

#else
#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
#endif

#if	defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)

#define	CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
#define	CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE

#else

#undef	CFG_SRAM_BASE
#undef	CFG_SRAM_SIZE

#endif

#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE

/*------------------------------------------------------------------------
 * MEMORY ORGANIZATION - For the most part, you can put things pretty
 * much anywhere. This is pretty flexible for Nios. So here we make some
 * arbitrary choices & assume that the monitor is placed at the end of
 * a memory resource (so you must make sure TEXT_BASE is chosen
 * appropriately -- this is very important if you plan to move your
 * memory to another place as configured at this time !!!).
 *
 * 	-The heap is placed below the monitor.
 * 	-Global data is placed below the heap.
 * 	-The stack is placed below global data (&grows down).
 *----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)

#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET

/*------------------------------------------------------------------------
 * FLASH (AM29LV065D)
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)

#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size	*/

#else
#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
#endif

/*------------------------------------------------------------------------
 * ENVIRONMENT
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)

#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */

/* Mem addr of environment */
#if	defined(CONFIG_NIOS_BASE_32)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
#else
#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
#endif

#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
#define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */

#else
#define	CFG_ENV_IS_NOWHERE	1		/* NO Environment	*/
#endif

/*------------------------------------------------------------------------
 * NIOS APPLICATION CODE BASE AREA
 *----------------------------------------------------------------------*/
#if	((CFG_ENV_ADDR + CFG_ENV_SIZE) == 0x1050000)
#define	CFG_ADNPESC1_UPDATE_LOAD_ADDR	"0x2000100"
#define CFG_ADNPESC1_NIOS_APPL_ENTRY	"0x1050000"
#define CFG_ADNPESC1_NIOS_APPL_IDENT	"0x105000c"
#define	CFG_ADNPESC1_NIOS_APPL_END	"0x11fffff"
#define CFG_ADNPESC1_FILESYSTEM_BASE	"0x1200000"
#define	CFG_ADNPESC1_FILESYSTEM_END	"0x17fffff"
#else
#error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h
#endif
#define CFG_ADNPESC1_NIOS_IDENTIFIER	"Nios"

/*------------------------------------------------------------------------
 * BOOT ENVIRONMENT
 *----------------------------------------------------------------------*/
#ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
#define	CFG_ADNPESC1_SLED_BOOT_OFF	"sled boot off; "
#define	CFG_ADNPESC1_SLED_RED_BLINK	"sled red blink; "
#else
#define	CFG_ADNPESC1_SLED_BOOT_OFF
#define	CFG_ADNPESC1_SLED_RED_BLINK
#endif

#define	CONFIG_BOOTDELAY	5
#define	CONFIG_BOOTCOMMAND						\
	"if itest.s *$appl_ident_addr == \"$appl_ident_str\"; "		\
	"then "								\
		"wd off; "						\
		CFG_ADNPESC1_SLED_BOOT_OFF				\
		"go $appl_entry_addr; "					\
	"else "								\
		CFG_ADNPESC1_SLED_RED_BLINK				\
		"echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\
		"echo *** invalid application at $appl_entry_addr; "	\
		"echo *** stop bootup...; "				\
	"fi"

/*------------------------------------------------------------------------
 * EXTRA ENVIRONMENT
 *----------------------------------------------------------------------*/
#ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
#define	CFG_ADNPESC1_SLED_YELLO_ON	"sled yellow on; "
#define	CFG_ADNPESC1_SLED_YELLO_OFF	"sled yellow off; "
#else
#define	CFG_ADNPESC1_SLED_YELLO_ON
#define	CFG_ADNPESC1_SLED_YELLO_OFF
#endif

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"update_allowed=0\0"						\
	"update_load_addr="	CFG_ADNPESC1_UPDATE_LOAD_ADDR	"\0"	\
	"appl_entry_addr="	CFG_ADNPESC1_NIOS_APPL_ENTRY	"\0"	\
	"appl_end_addr="	CFG_ADNPESC1_NIOS_APPL_END	"\0"	\
	"appl_ident_addr="	CFG_ADNPESC1_NIOS_APPL_IDENT	"\0"	\
	"appl_ident_str="	CFG_ADNPESC1_NIOS_IDENTIFIER	"\0"	\
	"appl_name=ADNPESC1/base32/linux.bin\0"				\
	"appl_update="							\
		"if itest.b $update_allowed != 0; "			\
		"then "							\
			CFG_ADNPESC1_SLED_YELLO_ON			\
			"tftp $update_load_addr $appl_name; "		\
			"protect off $appl_entry_addr $appl_end_addr; "	\
			"era $appl_entry_addr $appl_end_addr; "		\
			"cp.b $update_load_addr $appl_entry_addr $filesize; "\
			CFG_ADNPESC1_SLED_YELLO_OFF			\
		"else "							\
			"echo *** update not allowed (update_allowed=$update_allowed); "\
		"fi\0"							\
	"fs_base_addr="		CFG_ADNPESC1_FILESYSTEM_BASE	"\0"	\
	"fs_end_addr="		CFG_ADNPESC1_FILESYSTEM_END	"\0"	\
	"fs_name=ADNPESC1/base32/romfs.img\0"				\
	"fs_update="							\
		"if itest.b $update_allowed != 0; "			\
		"then "							\
			CFG_ADNPESC1_SLED_YELLO_ON			\
			"tftp $update_load_addr $fs_name; "		\
			"protect off $fs_base_addr $fs_end_addr; "	\
			"era $fs_base_addr $fs_end_addr; "		\
			"cp.b $update_load_addr $fs_base_addr $filesize; "\
			CFG_ADNPESC1_SLED_YELLO_OFF			\
		"else "							\
			"echo *** update not allowed (update_allowed=$update_allowed); "\
		"fi\0"							\
	"uboot_name=ADNPESC1/base32/u-boot.bin\0"			\
	"uboot_loadnrun="						\
		"if ping $serverip; "					\
		"then "							\
			CFG_ADNPESC1_SLED_YELLO_ON			\
			"tftp $update_load_addr $uboot_name; "		\
			"wd off; "					\
			"go $update_load_addr; "			\
		"else "							\
			"echo *** missing connection to $serverip; "	\
			"echo *** check your network and try again...; "\
		"fi\0"

/*------------------------------------------------------------------------
 * CONSOLE
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_UART_NUMS != 0)

#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */

#if	(CFG_NIOS_CPU_UART0_BR != 0)
#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
#else
#undef	CFG_NIOS_FIXEDBAUD
#define CONFIG_BAUDRATE		115200
#endif

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#else
#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
#endif

/*------------------------------------------------------------------------
 * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
 * so an avalon bus timer is required.
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)

#if	(CFG_NIOS_CPU_TICK_TIMER == 0)

#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ

#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */

#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
#else
#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
#endif

#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */

#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */

#if	(CFG_HZ <= 1000)
#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
#else
#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
#endif

#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)

#else
#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
#endif

#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)

#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ

#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */

#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
#else
#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
#endif

#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */

#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */

#if	(CFG_HZ <= 1000)
#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
#else
#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
#endif

#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)

#else
#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
#endif

#endif	/* CFG_NIOS_CPU_TICK_TIMER */

#else
#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
#endif

/*------------------------------------------------------------------------
 * WATCHDOG (or better MAX823 supervisory circuite access)
 *----------------------------------------------------------------------*/
#define	CONFIG_HW_WATCHDOG	1		/* board specific WD	*/

#ifdef	CONFIG_HW_WATCHDOG

/* MAX823 supervisor -- watchdog enable port at: */
#if	(CFG_NIOS_CPU_WDENA_PIO == 0)
#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO0	/* PIO0		*/
#elif	(CFG_NIOS_CPU_WDENA_PIO == 1)
#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO1	/* PIO1		*/
#elif	(CFG_NIOS_CPU_WDENA_PIO == 2)
#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO2	/* PIO2		*/
#elif	(CFG_NIOS_CPU_WDENA_PIO == 3)
#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO3	/* PIO3		*/
#elif	(CFG_NIOS_CPU_WDENA_PIO == 4)
#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO4	/* PIO4		*/
#elif	(CFG_NIOS_CPU_WDENA_PIO == 5)
#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO5	/* PIO5		*/
#elif	(CFG_NIOS_CPU_WDENA_PIO == 6)
#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO6	/* PIO6		*/
#elif	(CFG_NIOS_CPU_WDENA_PIO == 7)
#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO7	/* PIO7		*/