yucca.h

u-boot-1.1.6 源码包

#define CFG_FLASH_2ND_16BIT_DEV	1	/* evb440SPe has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR	0xe7c00000 /* evb440SPe has 8 and 16bit device*/

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
#define CFG_ENV_ADDR		0xfffa0000
/* #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
#define CFG_ENV_SIZE		0x10000	/* Size of Environment vars	*/
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
#undef CONFIG_PCI_CONFIG_HOST_BRIDGE

/* Board-specific PCI */
#define CFG_PCI_PRE_INIT	1	/* enable board pci_pre_init()	*/
#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
#undef	CFG_PCI_MASTER_INIT

#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
/* #define CFG_PCI_SUBSYS_ID	CFG_PCI_SUBSYS_DEVICEID */

/*
 *  NETWORK Support (PCI):
 */
/* Support for Intel 82557/82559/82559ER chips. */
#define CONFIG_EEPRO100

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/*Initial Memory map for Linux*/
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs		*/
#define CFG_CACHELINE_SIZE	32	/* ...				*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/* FB Divisor selection */
#define FPGA_FB_DIV_6		6
#define FPGA_FB_DIV_10		10
#define FPGA_FB_DIV_12		12
#define FPGA_FB_DIV_20		20

/* VCO Divisor selection */
#define	FPGA_VCO_DIV_4		4
#define	FPGA_VCO_DIV_6		6
#define	FPGA_VCO_DIV_8		8
#define	FPGA_VCO_DIV_10		10

/*----------------------------------------------------------------------------+
| FPGA registers and bit definitions
+----------------------------------------------------------------------------*/
/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
/* TLB initialization makes it correspond to logical address 0xE2000000. */
/* => Done init_chip.s in bootlib */
#define FPGA_REG_BASE_ADDR	0xE2000000
#define FPGA_GPIO_BASE_ADDR	0xE2010000
#define FPGA_INT_BASE_ADDR	0xE2020000

/*----------------------------------------------------------------------------+
| Display
+----------------------------------------------------------------------------*/
#define PPC440SPE_DISPLAY	FPGA_REG_BASE_ADDR

#define PPC440SPE_DISPLAY_D8	(FPGA_REG_BASE_ADDR+0x06)
#define PPC440SPE_DISPLAY_D4	(FPGA_REG_BASE_ADDR+0x04)
#define PPC440SPE_DISPLAY_D2	(FPGA_REG_BASE_ADDR+0x02)
#define PPC440SPE_DISPLAY_D1	(FPGA_REG_BASE_ADDR+0x00)
/*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
/*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/

/*----------------------------------------------------------------------------+
| ethernet/reset/boot Register 1
+----------------------------------------------------------------------------*/
#define FPGA_REG10	(FPGA_REG_BASE_ADDR+0x10)

#define FPGA_REG10_10MHZ_ENABLE		0x8000
#define FPGA_REG10_100MHZ_ENABLE	0x4000
#define FPGA_REG10_GIGABIT_ENABLE	0x2000
#define FPGA_REG10_FULL_DUPLEX		0x1000	/* force Full Duplex*/
#define FPGA_REG10_RESET_ETH		0x0800
#define FPGA_REG10_AUTO_NEG_DIS		0x0400
#define FPGA_REG10_INTP_ETH		0x0200

#define FPGA_REG10_RESET_HISR		0x0080
#define FPGA_REG10_ENABLE_DISPLAY	0x0040
#define FPGA_REG10_RESET_SDRAM		0x0020
#define FPGA_REG10_OPER_BOOT		0x0010
#define FPGA_REG10_SRAM_BOOT		0x0008
#define FPGA_REG10_SMALL_BOOT		0x0004
#define FPGA_REG10_FORCE_COLA		0x0002
#define FPGA_REG10_COLA_MANUAL		0x0001

#define FPGA_REG10_SDRAM_ENABLE		0x0020

#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/

/*----------------------------------------------------------------------------+
| MUX control
+----------------------------------------------------------------------------*/
#define FPGA_REG12	(FPGA_REG_BASE_ADDR+0x12)

#define FPGA_REG12_EBC_CTL		0x8000
#define FPGA_REG12_UART1_CTS_RTS	0x4000
#define FPGA_REG12_UART0_RX_ENABLE	0x2000
#define FPGA_REG12_UART1_RX_ENABLE	0x1000
#define FPGA_REG12_UART2_RX_ENABLE	0x0800
#define FPGA_REG12_EBC_OUT_ENABLE	0x0400
#define FPGA_REG12_GPIO0_OUT_ENABLE	0x0200
#define FPGA_REG12_GPIO1_OUT_ENABLE	0x0100
#define FPGA_REG12_GPIO_SELECT		0x0010
#define FPGA_REG12_GPIO_CHREG		0x0008
#define FPGA_REG12_GPIO_CLK_CHREG	0x0004
#define FPGA_REG12_GPIO_OETRI		0x0002
#define FPGA_REG12_EBC_ERROR		0x0001

/*----------------------------------------------------------------------------+
| PCI Clock control
+----------------------------------------------------------------------------*/
#define FPGA_REG16	(FPGA_REG_BASE_ADDR+0x16)

#define FPGA_REG16_PCI_CLK_CTL0		0x8000
#define FPGA_REG16_PCI_CLK_CTL1		0x4000
#define FPGA_REG16_PCI_CLK_CTL2		0x2000
#define FPGA_REG16_PCI_CLK_CTL3		0x1000
#define FPGA_REG16_PCI_CLK_CTL4		0x0800
#define FPGA_REG16_PCI_CLK_CTL5		0x0400
#define FPGA_REG16_PCI_CLK_CTL6		0x0200
#define FPGA_REG16_PCI_CLK_CTL7		0x0100
#define FPGA_REG16_PCI_CLK_CTL8		0x0080
#define FPGA_REG16_PCI_CLK_CTL9		0x0040
#define FPGA_REG16_PCI_EXT_ARB0		0x0020
#define FPGA_REG16_PCI_MODE_1		0x0010
#define FPGA_REG16_PCI_TARGET_MODE	0x0008
#define FPGA_REG16_PCI_INTP_MODE	0x0004

/* FB1 Divisor selection */
#define FPGA_REG16_FB2_DIV_MASK		0x1000
#define FPGA_REG16_FB2_DIV_LOW		0x0000
#define FPGA_REG16_FB2_DIV_HIGH		0x1000
/* FB2 Divisor selection */
/* S3 switch on Board */
#define FPGA_REG16_FB1_DIV_MASK		0x2000
#define FPGA_REG16_FB1_DIV_LOW		0x0000
#define FPGA_REG16_FB1_DIV_HIGH		0x2000
/* PCI0 Clock Selection */
/* S3 switch on Board */
#define FPGA_REG16_PCI0_CLK_MASK	0x0c00
#define FPGA_REG16_PCI0_CLK_33_33	0x0000
#define FPGA_REG16_PCI0_CLK_66_66	0x0800
#define FPGA_REG16_PCI0_CLK_100		0x0400
#define FPGA_REG16_PCI0_CLK_133_33	0x0c00
/* VCO Divisor selection */
/* S3 switch on Board */
#define FPGA_REG16_VCO_DIV_MASK		0xc000
#define FPGA_REG16_VCO_DIV_4		0x0000
#define FPGA_REG16_VCO_DIV_8		0x4000
#define FPGA_REG16_VCO_DIV_6		0x8000
#define FPGA_REG16_VCO_DIV_10		0xc000
/* Master Clock Selection */
/* S3, S4 switches on Board */
#define FPGA_REG16_MASTER_CLK_MASK	0x01c0
#define FPGA_REG16_MASTER_CLK_EXT	0x0000
#define FPGA_REG16_MASTER_CLK_66_66	0x0040
#define FPGA_REG16_MASTER_CLK_50	0x0080
#define FPGA_REG16_MASTER_CLK_33_33	0x00c0
#define FPGA_REG16_MASTER_CLK_25	0x0100

/*----------------------------------------------------------------------------+
| PCI Miscellaneous
+----------------------------------------------------------------------------*/
#define FPGA_REG18	(FPGA_REG_BASE_ADDR+0x18)

#define FPGA_REG18_PCI_PRSNT1		0x8000
#define FPGA_REG18_PCI_PRSNT2		0x4000
#define FPGA_REG18_PCI_INTA		0x2000
#define FPGA_REG18_PCI_SLOT0_INTP	0x1000
#define FPGA_REG18_PCI_SLOT1_INTP	0x0800
#define FPGA_REG18_PCI_SLOT2_INTP	0x0400
#define FPGA_REG18_PCI_SLOT3_INTP	0x0200
#define FPGA_REG18_PCI_PCI0_VC		0x0100
#define FPGA_REG18_PCI_PCI0_VTH1	0x0080
#define FPGA_REG18_PCI_PCI0_VTH2	0x0040
#define FPGA_REG18_PCI_PCI0_VTH3	0x0020

/*----------------------------------------------------------------------------+
| PCIe Miscellaneous
+----------------------------------------------------------------------------*/
#define FPGA_REG1A	(FPGA_REG_BASE_ADDR+0x1A)

#define FPGA_REG1A_PE0_GLED		0x8000
#define FPGA_REG1A_PE1_GLED		0x4000
#define FPGA_REG1A_PE2_GLED		0x2000
#define FPGA_REG1A_PE0_YLED		0x1000
#define FPGA_REG1A_PE1_YLED		0x0800
#define FPGA_REG1A_PE2_YLED		0x0400
#define FPGA_REG1A_PE0_PWRON		0x0200
#define FPGA_REG1A_PE1_PWRON		0x0100
#define FPGA_REG1A_PE2_PWRON		0x0080
#define FPGA_REG1A_PE0_REFCLK_ENABLE	0x0040
#define FPGA_REG1A_PE1_REFCLK_ENABLE	0x0020
#define FPGA_REG1A_PE2_REFCLK_ENABLE	0x0010
#define FPGA_REG1A_PE_SPREAD0		0x0008
#define FPGA_REG1A_PE_SPREAD1		0x0004
#define FPGA_REG1A_PE_SELSOURCE_0	0x0002
#define FPGA_REG1A_PE_SELSOURCE_1	0x0001

/*----------------------------------------------------------------------------+
| PCIe Miscellaneous
+----------------------------------------------------------------------------*/
#define FPGA_REG1C	(FPGA_REG_BASE_ADDR+0x1C)

#define FPGA_REG1C_PE0_ROOTPOINT	0x8000
#define FPGA_REG1C_PE1_ENDPOINT		0x4000
#define FPGA_REG1C_PE2_ENDPOINT		0x2000
#define FPGA_REG1C_PE0_PRSNT		0x1000
#define FPGA_REG1C_PE1_PRSNT		0x0800
#define FPGA_REG1C_PE2_PRSNT		0x0400
#define FPGA_REG1C_PE0_WAKE		0x0080
#define FPGA_REG1C_PE1_WAKE		0x0040
#define FPGA_REG1C_PE2_WAKE		0x0020
#define FPGA_REG1C_PE0_PERST		0x0010
#define FPGA_REG1C_PE1_PERST		0x0008
#define FPGA_REG1C_PE2_PERST		0x0004

/*----------------------------------------------------------------------------+
| Defines
+----------------------------------------------------------------------------*/
#define PERIOD_133_33MHZ	7500	/* 7,5ns */
#define PERIOD_100_00MHZ	10000	/* 10ns */
#define PERIOD_83_33MHZ		12000	/* 12ns */
#define PERIOD_75_00MHZ		13333	/* 13,333ns */
#define PERIOD_66_66MHZ		15000	/* 15ns */
#define PERIOD_50_00MHZ		20000	/* 20ns */
#define PERIOD_33_33MHZ		30000	/* 30ns */
#define PERIOD_25_00MHZ		40000	/* 40ns */

/*---------------------------------------------------------------------------*/

#endif	/* __CONFIG_H */