exalion.h

u-boot-1.1.6 源码包

#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2	/* for MPC8240 only		*/

				       /*#define CONFIG_133MHZ_DRAM	 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!!    */

#if defined (CONFIG_MPC8245)
/* Bit-field values for PMCR2.							*/
#if defined (CONFIG_133MHZ_DRAM)
#define CFG_DLL_EXTEND		0x80	/* use DLL extended range - 133MHz only */
#define CFG_PCI_HOLD_DEL	0x20	/* delay and hold timing - 133MHz only	*/
#endif

/* Bit-field values for MIOCR1.							*/
#if !defined (CONFIG_133MHZ_DRAM)
#define CFG_DLL_MAX_DELAY	0x04	/*  longer DLL delay line - 66MHz only	*/
#endif
/* Bit-field values for MIOCR2.							*/
#define CFG_SDRAM_DSCD		0x20	/* SDRAM data in sample clock delay	*/
					/*	- note bottom 3 bits MUST be 0	*/
#endif

/* Bit-field values for MCCR1.							*/
#define CFG_ROMNAL		7	/*rom/flash next access time		*/
#define CFG_ROMFAL	       11	/*rom/flash access time			*/

/* Bit-field values for MCCR2.							*/
#define CFG_TSWAIT		0x5	/* Transaction Start Wait States timer	*/
#if defined (CONFIG_133MHZ_DRAM)
#define CFG_REFINT		1300	/* no of clock cycles between CBR	*/
#else  /* refresh cycles */
#define CFG_REFINT		750
#endif

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.		*/
#if defined (CONFIG_133MHZ_DRAM)
#define CFG_BSTOPRE		1023
#else
#define CFG_BSTOPRE		250
#endif

/* Bit-field values for MCCR3.							*/
/* the following are for SDRAM only						*/

#if defined (CONFIG_133MHZ_DRAM)
#define CFG_REFREC		9	/* Refresh to activate interval		*/
#else
#define CFG_REFREC		5	/* Refresh to activate interval		*/
#endif
#if defined (CONFIG_MPC8240)
#define CFG_RDLAT		2	/* data latency from read command	*/
#endif

/* Bit-field values for MCCR4.	*/
#if defined (CONFIG_133MHZ_DRAM)
#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
#define CFG_ACTTOPRE		7	/* Activate to Precharge interval	*/
#define CFG_ACTORW		5	/* Activate to R/W			*/
#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#else
#if 0
#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
#define CFG_ACTTOPRE		3	/* Activate to Precharge interval	*/
#define CFG_ACTORW		3	/* Activate to R/W			*/
#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
#endif
#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
#define CFG_ACTORW		3	/* Activate to R/W			*/
#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#endif
#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
#define CFG_REGDIMM		0
#if defined (CONFIG_MPC8240)
#define CFG_REGISTERD_TYPE_BUFFER   0
#elif defined (CONFIG_MPC8245)
#define CFG_REGISTERD_TYPE_BUFFER   1
#define CFG_EXTROM		    0
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif


/*-----------------------------------------------------------------------
 memory bank settings
 * only bits 20-29 are actually used from these vales to set the
 * start/end address the upper two bits will be 0, and the lower 20
 * bits will be set to 0x00000 for a start address, or 0xfffff for an
 * end address
 */
#define CFG_BANK0_START		0x00000000
#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE	1
#define CFG_BANK1_START		0x3ff00000
#define CFG_BANK1_END		0x3fffffff
#define CFG_BANK1_ENABLE	0
#define CFG_BANK2_START		0x3ff00000
#define CFG_BANK2_END		0x3fffffff
#define CFG_BANK2_ENABLE	0
#define CFG_BANK3_START		0x3ff00000
#define CFG_BANK3_END		0x3fffffff
#define CFG_BANK3_ENABLE	0
#define CFG_BANK4_START		0x00000000
#define CFG_BANK4_END		0x00000000
#define CFG_BANK4_ENABLE	0
#define CFG_BANK5_START		0x00000000
#define CFG_BANK5_END		0x00000000
#define CFG_BANK5_ENABLE	0
#define CFG_BANK6_START		0x00000000
#define CFG_BANK6_END		0x00000000
#define CFG_BANK6_ENABLE	0
#define CFG_BANK7_START		0x00000000
#define CFG_BANK7_END		0x00000000
#define CFG_BANK7_ENABLE	0

/*-----------------------------------------------------------------------
 * Memory bank enable bitmask, specifying which of the banks defined above
 are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CFG_BANK_ENABLE		0x01

#if defined (CONFIG_MPC8240)
#define CFG_ODCR		0xDF	/* configures line driver impedances,	*/
					/* see 8240 book for bit definitions	*/
#elif defined (CONFIG_MPC8245)
#if defined (CONFIG_133MHZ_DRAM)
#define CFG_ODCR		0xFE	/* configures line driver impedances - 133MHz	*/
#else
#define CFG_ODCR		0xDE	/* configures line driver impedances - 66MHz	*/
#endif
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

/*-----------------------------------------------------------------------
 * Block Address Translation (BAT) register settings.
 */
/* SDRAM 0 - 256MB */
#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE @ 1GB (no backing mem) */
#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

/* PCI memory */
#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* Flash, config addrs, etc */
#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U
#define CFG_DBAT1L	CFG_IBAT1L
#define CFG_DBAT1U	CFG_IBAT1U
#define CFG_DBAT2L	CFG_IBAT2L
#define CFG_DBAT2U	CFG_IBAT2U
#define CFG_DBAT3L	CFG_IBAT3L
#define CFG_DBAT3U	CFG_IBAT3U


/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


/*-----------------------------------------------------------------------
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/


/* values according to the manual */
#define CONFIG_DRAM_50MHZ	1
#define CONFIG_SDRAM_50MHZ

#undef	NR_8259_INTS
#define NR_8259_INTS		1

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 */
#define CFG_IDE_MAXBUS	    1	/* max. 2 IDE busses	*/
#define CFG_IDE_MAXDEVICE   (CFG_IDE_MAXBUS*1)	/* max. 2 drives per IDE bus */

#define CFG_ATA_BASE_ADDR   CFG_ISA_IO	/* base address */
#define CFG_ATA_IDE0_OFFSET 0x01F0	/* ide0 offste */
#define CFG_ATA_IDE1_OFFSET 0x0170	/* ide1 offset */
#define CFG_ATA_DATA_OFFSET 0	/* data reg offset  */
#define CFG_ATA_REG_OFFSET  0	/* reg offset */
#define CFG_ATA_ALT_OFFSET  0x200	/* alternate register offset */

#define CONFIG_ATAPI

#undef	CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
#undef	CONFIG_IDE_LED		/* no led for ide supported	*/
#undef	CONFIG_IDE_RESET	/* reset for ide supported...	 */
#undef	CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */

/*-----------------------------------------------------------------------
 * DISK Partition support
 */
#define CONFIG_DOS_PARTITION

/*-----------------------------------------------------------------------
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#endif /* __CONFIG_H */