xaeniax.h

u-boot-1.1.6 源码包

/*
 * (C) Copyright 2004-2005
 * Wolfgang Denk, DENX Software Engineering, <[e-mail]>
 *
 * (C) Copyright 2004
 * Vincent Dubey, Xa SA, [e-mail]
 *
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. [e-mail]
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <[e-mail]>
 *
 * Configuation settings for the xaeniax board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
#define CONFIG_XAENIAX		1	/* on a xaeniax board	    */


#define BOARD_LATE_INIT		1


#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

/*
 * select serial console configuration
 */
#define CONFIG_BTUART	       1       /* we use BTUART on XAENIAX */


/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

#define CONFIG_BAUDRATE		115200

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */

#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL & ~CFG_CMD_DTT) | \
				CFG_CMD_DHCP	| \
				CFG_CMD_DIAG	| \
				CFG_CMD_NFS	| \
				CFG_CMD_SDRAM	| \
				CFG_CMD_SNTP	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.68.201
#define CONFIG_SERVERIP		192.168.68.62

#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTCOMMAND	"bootm 0x00100000"
#define CONFIG_BOOTARGS		"console=ttyS1,115200"
#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 	1
#define CONFIG_INITRD_TAG		1

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200			/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	1			/* which serial port to use */
#endif

/*
 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
 * used for the RAM copy of the uboot code
 */
#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP				/* undef to save memory	*/
#define CFG_HUSH_PARSER		1

#define CFG_PROMPT_HUSH_PS2	"> "

#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT		"u-boot$ "	/* Monitor Command Prompt */
#else
#define CFG_PROMPT		"u-boot=> "	/* Monitor Command Prompt */
#endif
#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_DEVICE_NULLDEV	1

#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/

#undef	CFG_CLKS_IN_HZ				/* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR		0xa1000000	/* default load address */

#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
#define CFG_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks (partition) of DRAM */
#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */

#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */

#define CFG_DRAM_BASE		0xa0000000
#define CFG_DRAM_SIZE		0x04000000

#define CFG_FLASH_BASE		PHYS_FLASH_1

/*
 * FLASH and environment organization
 */
#define CFG_MAX_FLASH_BANKS	1    /* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */

/* FIXME */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector	*/
#define CFG_ENV_SIZE		0x40000			/* Total Size of Environment Sector	*/

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*
 * SMSC91C111 Network Card
 */
#define CONFIG_DRIVER_SMC91111		1
#define CONFIG_SMC91111_BASE		0x10000300  /* chip select 3         */
#define CONFIG_SMC_USE_32_BIT		1          /* 32 bit bus  */
#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
#undef  CONFIG_SHOW_ACTIVITY
#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */

/*
 * GPIO settings
 */

/*
 * GP05 == nUSBReset  is 1
 * GP10 == CFReset   is 1
 * GP13 == nCFDataEnable is 1
 * GP14 == nCFAddrEnable is 1
 * GP15 == nCS1      is 1
 * GP21 == ComBrdReset is 1
 * GP24 == SFRM      is 1
 * GP25 == TXD       is 1
 * GP31 == SYNC      is 1
 * GP33 == nCS5      is 1
 * GP39 == FFTXD     is 1
 * GP41 == RTS       is 1
 * GP43 == BTTXD     is 1
 * GP45 == BTRTS     is 1
 * GP47 == TXD       is 1
 * GP48 == nPOE      is 1
 * GP49 == nPWE      is 1
 * GP50 == nPIOR     is 1
 * GP51 == nPIOW     is 1
 * GP52 == nPCE[1]   is 1
 * GP53 == nPCE[2]   is 1
 * GP54 == nPSKTSEL  is 1
 * GP55 == nPREG     is 1
 * GP78 == nCS2      is 1
 * GP79 == nCS3      is 1
 * GP80 == nCS4      is 1
 * GP82 == NSSPSFRM  is 1
 * GP83 == NSSPTXD   is 1
 */
#define CFG_GPSR0_VAL		0x8320E420
#define CFG_GPSR1_VAL		0x00FFAA82
#define CFG_GPSR2_VAL		0x000DC000

/*
 * GP03 == LANReset  is 0
 * GP06 == USBWakeUp  is 0
 * GP11 == USBControl is 0
 * GP12 == Buzzer     is 0
 * GP16 == PWM0       is 0
 * GP17 == PWM1       is 0
 * GP23 == SCLK      is 0
 * GP30 == SDATA_OUT is 0
 * GP81 == NSSPCLK   is 0
 */
#define CFG_GPCR0_VAL		0x40C31848
#define CFG_GPCR1_VAL		0x00000000
#define CFG_GPCR2_VAL		0x00020000

/*
 * GP00 == CPUWakeUpUSB is input
 * GP01 == GP reset is input
 * GP02 == LANInterrupt is input
 * GP03 == LANReset     is output
 * GP04 == USBInterrupt is input
 * GP05 == nUSBReset    is output
 * GP06 == USBWakeUp    is output
 * GP07 == CFReady/nBusy is input
 * GP08 == nCFCardDetect1 is input
 * GP09 == nCFCardDetect2 is input
 * GP10 == nCFReset   is output
 * GP11 == USBControl is output
 * GP12 == Buzzer     is output
 * GP13 == CFDataEnable is output
 * GP14 == CFAddressEnable is output
 * GP15 == nCS1      is output
 * GP16 == PWM0      is output
 * GP17 == PWM1      is output
 * GP18 == RDY       is input
 * GP19 == ReaderReady is input
 * GP20 == ReaderReset is input
 * GP21 == ComBrdReset is output
 * GP23 == SCLK      is output
 * GP24 == SFRM      is output
 * GP25 == TXD       is output
 * GP26 == RXD       is input
 * GP27 == EXTCLK    is input
 * GP28 == BITCLK    is output
 * GP29 == SDATA_IN0 is input
 * GP30 == SDATA_OUT is output
 * GP31 == SYNC      is output
 * GP32 == SYSSCLK   is output
 * GP33 == nCS5      is output
 * GP34 == FFRXD     is input
 * GP35 == CTS       is input
 * GP36 == DCD       is input